CMOS cell and circuit design for improved IDDQ testing

Details CMOS cell and circuit design for improved IDDQ testing CMOS cell and circuit design for improved IDDQ testing

2000-08-23

2001-10-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C324S763010, C324S765010, C324S762010, C714S718000

Reexamination Certificate

active

06301168

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to CMOS technology and IDDQ test methodology, and more particularly to CMOS cell and circuit design for improved IDDQ testing of CMOS logic circuits and CMOS memories.
RELATED ART
CMOS is the technology of choice for many circuit and system designers for various reasons, including low quiescent power dissipation and potentially high speed operation. It is noted that although CMOS technology originally referred to devices made with metal, the terms “CMOS”, “PMOS”, “NMOS” and “MOS-type” refer generally to all types of CMOS technology including those made more recently with poly-crystalline silicon, or polysilicon, rather than metal. As with any logic circuit or functional system, a design implemented with CMOS technology must be tested to insure proper operation. Many different type of tests are employed for verifing circuit operation and integrity. For example, many different types of functional tests are employed to ensure proper functional operation of the logic circuit. For memory arrays or circuits, many different types of memory tests are known for testing the functional aspects of the memory cells.
For CMOS circuits including logic and memory circuits, one particular type of test is known as static Idd test or the IDDQ test. During the typical IDDQ test, power is applied via power supply voltage terminals and a multitude of test vectors are applied at the inputs while the quiescent drain current of the circuit is measured or otherwise sampled. Even for relatively large circuits, such as Very Large Scale Integration (VLSI) circuits or the like including thousands or millions of transistors, the static drain current should be relatively low. If the sampled current of the circuit is appreciably high for any particular test vector, then the device under test fails the IDDQ test.
In particular, the CMOS circuit includes NMOS and PMOS transistors, each with gate-to-source, gate-to-drain and gate-to-substrate interfaces, collectively referred to as the gate oxide interfaces. These gate oxide interfaces are substantially capacitive in nature and normally draw a very low amount of drain current when a test voltage is applied across the interface. If the gate oxide interface fails for any reason, it typically becomes a resistive interface with a low resistance so that it draws a significantly high level of current when voltage is applied. The IDDQ test is utilized in an attempt to identify any failed portions of a CMOS circuit including any failed gate oxide interfaces. A single failed gate oxide interface causes failure of the entire CMOS circuit if it receives a test voltage during the IDDQ test.
A substantial problem of the IDDQ test for CMOS technology is that it is difficult, if not virtually impossible, to test each gate oxide interface of each transistor. The inputs to the logic circuit, generally referred to as the primary inputs, do not access every transistor or even every logic cell or macro cell within the CMOS circuit. For this reason, test engineers attempt to test as many gate oxide interfaces as possible by utilizing a multitude of test vectors applied at the primary inputs. For most circuits, however, particularly large circuit designs, a prohibitive number of test vectors would have to be applied at the primary inputs to test every gate oxide interface of the circuit. Test methodologies have been designed and utilized to minimize the number of test vectors and to simultaneously maximize the number of gate oxide interfaces that are tested during the IDDQ test. Nonetheless, even the most aggressive test methodologies utilize hundreds or thousands of test vectors thereby consuming an appreciable amount of time to conduct the IDDQ test. Furthermore, virtually none of the these test methodologies is capable of testing all gate oxide interfaces. A CMOS circuit with a failed gate oxide interface may not receive a test voltage during the IDDQ test in spite of the multitude of test vectors, and thereby go undetected.


REFERENCES:
patent: 6144214 (2000-11-01), Athan
patent: 6184048 (2001-02-01), Ramon

Affiliated with

Also associated with

Rating

CMOS cell and circuit design for improved IDDQ testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS cell and circuit design for improved IDDQ testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS cell and circuit design for improved IDDQ testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2576174