Circuits, systems and methods for testing integrated circuit dev

Details Circuits, systems and methods for testing integrated circuit dev Circuits, systems and methods for testing integrated circuit dev

1995-06-30

1996-07-09

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518905, 365198, 371 211, 371 221, G11C 700, G11C 2900, G01R 3128

Patent

active

055351654

ABSTRACT:
A single chip integrated circuit 200 is disclosed which includes logic circuitry 202, memory circuitry 204, and a bus 300. First bus control circuitry 302 controls the exchange of signals between logic circuitry 202 and bus 300. Second bus control circuitry 303 controls the exchange of signals between memory circuitry 204 and bus 300. Third bus control circuitry 306 is included which controls the exchange of signals between bus 300 and at least one test pin 206. Mode control circuitry 205 is operable as control circuitry 302, 303, and 306. In the operating mode, mode control circuitry 205 activates first bus control circuitry 302 and second bus control circuitry 303. In a memory test mode, mode control circuitry 205 activates second bus control circuitry 303 and third bus control circuitry 306 and deactivates first bus control circuitry 302. In a logic test mode, test mode circuitry 205 activates first bus control circuitry 302 and third bus control circuitry 306 and deactivates second bus control circuitry 303.

REFERENCES:
patent: 4672583 (1987-06-01), Nakaizumi
patent: 4956518 (1990-09-01), Hatayama et al.
patent: 5047711 (1991-09-01), Smith et al.
patent: 5134587 (1992-07-01), Steele
patent: 5383193 (1995-01-01), Pazhak et al.
patent: 5414352 (1995-05-01), Tanase

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