Circuit structure and method for stress testing of bit lines

Details Circuit structure and method for stress testing of bit lines Circuit structure and method for stress testing of bit lines

1994-10-31

1997-03-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365 51, 365200, G11C 1300

Patent

active

056108664

ABSTRACT:
A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.

REFERENCES:
patent: 4007452 (1977-02-01), Hoff
patent: 4233674 (1980-11-01), Russell et al.

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