Architecture of a non-volatile electrically erasable and...
Architecture of a nvDRAM array and its sense regime
Architecture to suppress bit-line leakage
Area efficient implementation of small blocks in an SRAM array
Arrangement for storing a count
Array and pitch of non-volatile memory cells
Array architecture and operation methods for a nonvolatile...
Array cell circuit with split read/write line
Array structure of two-transistor cells with merged floating...
Array VSS biasing for NAND array programming reliability
Array-source line, bitline and wordline sequence in flash operat
Auto adjusting window placement scheme for an NROM virtual...
Auto-saving circuit for programming configuration elements in no
Avalanche programmed floating gate memory cell structure with pr
Bandgap engineered split gate memory
Bias circuit for virtual ground non-volatile memory array with b
Bias scheme of program inhibit for random programming in a nand
Bit line biasing method to eliminate program disturbance in a no
BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE...
Bit line gate transistor structure for a multilevel,...