Array cell circuit with split read/write line

Details Array cell circuit with split read/write line Array cell circuit with split read/write line

1996-05-06

1998-05-05

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518501, 36518517, 36518522, 36518518, 36523006, 257316, 257319, 257320, 257322, G11C 1606

Patent

active

057485259

ABSTRACT:
A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.

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