Bias circuit for virtual ground non-volatile memory array with b

Details Bias circuit for virtual ground non-volatile memory array with b Bias circuit for virtual ground non-volatile memory array with b

1994-09-09

1996-05-14

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36523002, 36523003, G11C 1134

Patent

active

055174485

ABSTRACT:
A bias circuit for virtual ground non-volatile memory array with bank selector, utilizes static pull-up transistors connected respectively to all bit lines of the memory array. The gates of the static pull-up transistors are connected to a predetermined reference voltage for supplying a global bias voltage to the bit lines. Another predetermined reference voltage, acting as a local bias voltage, is supplied to a deselected virtual ground bit line which is adjacent to the selected data sense bit line. By these two bias techniques, the leakage current of the adjacent deselected "ON" memory cells is minimized; as a result, the stability of the current detector is largely enhanced; the probability of erroneous data reading is reduced; the operating voltage margin of the memory devices is enlarged; and the data accessing is expedited.

REFERENCES:
patent: 4281397 (1981-07-01), Neal et al.
patent: 5132933 (1992-07-01), Schreck et al.

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