Area efficient implementation of small blocks in an SRAM array

Details Area efficient implementation of small blocks in an SRAM array Area efficient implementation of small blocks in an SRAM array

2007-06-26

2007-06-26

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S154000, C365S185110

Reexamination Certificate

active

11171033

ABSTRACT:
An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

REFERENCES:
patent: 5923593 (1999-07-01), Hsu et al.
patent: 6295222 (2001-09-01), Higashide et al.
patent: 6363027 (2002-03-01), Komatsu
patent: 6768144 (2004-07-01), Houston et al.
patent: 2005/0281098 (2005-12-01), Sadra et al.
Fukaura et al., “A Highly Manufacturable High Density embedded SRAM Technology for 90nm CMOS,” IEDM 2002.

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