Architecture to suppress bit-line leakage

Details Architecture to suppress bit-line leakage Architecture to suppress bit-line leakage

2002-12-13

2004-11-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185270

Reexamination Certificate

active

06819593

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method to improve a nonvolatile memory cell, and, more particularly, to a method to suppress bit-line leakage in a nonvolatile memory cell.
(2) Description of the Prior Art
Nonvolatile memory, such as EEPROM and Flash EEPROM, is used in many electronics applications. Nonvolatile memory combines the capability of writing data and maintaining data during power down. It is typical in the art for nonvolatile memory arrays to comprise thousands of even millions of memory cells.
Referring now to
FIG. 1
, an exemplary flash memory cell
10
is shown in cross section representation. As is common in the art, the flash memory cell
10
comprises two transistors having separate bit lines
18
and a common source
22
. Each transistor forms a single storage bit of memory. Each transistor further comprises a floating gate electrode
34
and a control gate electrode
38
. The flash transistors are turned ON or OFF based on the voltage on the control gates
26
and
30
. The amount of charge trapped on the floating gates
34
determines the threshold voltages of the two devices. Charge is moved onto or off of the floating gates by biasing the control gates
38
, bit lines
18
, and source line
22
to cause a large voltage potential from floating gate
34
to substrate
14
or to control gate
38
.
Further, the flash cells
10
are typically formed in arrays of devices across the wafer substrate
14
. These cells are coupled to form units of memory such as bytes, words, or pages, as is well known in the art. In a typical arrangement, the control gates
38
of a row or column of cells are coupled together such that group of control gates
38
forms a word line that is selected as a group. In addition, in a typical arrangement, the common source connection
22
between a pair of cells is also shared with other cells in the local array.
To read a flash bit, the word line is biased to a reading voltage while a small bias is forced from bit line
18
to source
22
. The current flow through the transistor is then sensed to determine if the transistor has been turned ON. In this way, the voltage threshold, relative to the reading voltage, can be determined, and the floating gate state (charged or non-charged) can be deduced.
The floating gate
34
and control gate
38
of the flash transistors may be formed as a stacked gate or as a split gate. In a stacked gate, the control gate overlies the flash gate but does not otherwise overlie the substrate
14
. In a stacked gate flash or EEPROM transistor, the channel region is formed only underlying the floating gate. In a split gate device, the control gate may be formed to couple charge onto the floating gate and to overlie the substrate. In this way, the control gate
38
can control a part of the transistor channel. The exemplary flash cell of
FIG. 1
shows split gate transistors. A circuit symbol for a flash transistor
40
is also illustrated.
Referring now to
FIG. 2
, an exemplary array
50
of flash cells is illustrated. In this array
50
, each flash transistor is represented by the circuit symbol introduced in FIG.
1
. Several features of the array should be noted. First, the common sources between a pair of cells, such as C
00
and C
01
, are further coupled to a common VSS signal. The VSS signal is the common source for the entire array
50
. The bit line signals BL
0
, BL
1
, and BL
2
are coupled to all of the bit line terminals of a given row of cells. However, each row has an independent bit line. The word line signals WL
0
, WL
1
, WL
2
, and WL
3
are coupled to all of the control gates in a given column. However, each column has a separate word line.
In this configuration, it is possible to address a particular cell of the array
50
by selecting a single bit line and a single word line. Erasing operating conditions are particularly shown in FIG.
2
. The word lines, bit lines, and common source are biased such that cell C
12
66
is selected for erasing. In particular, BL
1
is driven to a selection voltage of about 0.5 Volts while BL
0
and BL
2
are driven to a non-selection voltage of about 1.65 Volts. Further, WL
2
is driven to a selection voltage of about 1.5 Volts while WL
0
, WL
1
, and WL
3
are driven to non-selection voltages of about 0 Volts. Finally, the common source lines VSS are all driven to about 7 Volts. In this state, the selected transistor C
12
66
is biased to cause a discharge of electrons from the floating gate.
Note that all of the cells within the array
50
are also effected by the erasing operation. For example, all of the transistors in the WL
2
column will also see the selection voltage on the control gate. Therefore, cells C
02
56
and C
22
76
will experience word line disturbance. All of the cells coupled to BL
1
will see the selection voltage on the bit line node. Therefore, cells C
10
62
, C
11
64
, and C
13
68
will experience bit line disturbance. All of the cells in the page will see the selection voltage on the common source VSS. Therefore, cells not in the row or column with the selected cell will experience the elevated large VSS voltage of about 7 Volts during the erase.
It is further found that the array
50
may comprise a subsection, or page, of the larger memory array. Yet, it is common in such arrays to couple a large number of cell bit line regions to common bit line signals. For example, BL
0
signal may be coupled to several array pages across the memory. The combination of a bit line selected and a word line selected will cause selection of the correct cell for erasing, programming, or reading. However, to reduce the source line stress on unselected cells, the common VSS voltage is set to zero volts in the non-selected pages of memory. This approach has an unintended consequence, however. It is found that bit line leakage in these non-selected cells can occur. Since there are many such non-selected cells, the combined leakage current can be unacceptably large.
Several prior art inventions relate to nonvolatile memory devices. U.S. Pat. No. 6,285,593 B1 to Wong discloses a word line decoder for a multiple level memory. Leakage current is reduced by applying a negative voltage to unselected word lines. Selected or unselected word lines are held at ground. U.S. Pat. No. 5,808,338 to Gotou describes a nonvolatile semiconductor memory. U.S. Pat. No. 5,838,617 to Bude et al discloses a method to program EPROM or EEPROM devices. A negative substrate bias is used. U.S. Pat. No. 6,046,932 to Bill et al shows a circuit to reduce bit line current during programming or overerase correction. A resistance is added to the common source line.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective method to reduce bit line leakage in a nonvolatile memory device.
A further object of the present invention is to provide a method reduce bit line leakage in non-selected cells of a nonvolatile memory device by providing a non-zero common source to substrate voltage.
Another object of the present invention is to provide a nonvolatile memory device having a reduced bit line leakage.
A further object of the present invention is to reduce bit line leakage in non-selected cells of a nonvolatile memory device by providing a non-zero common source to substrate voltage.
In accordance with the objects of this invention, a method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and th

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