BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE...

Details BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE... BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE...

2002-09-27

2004-06-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185180

Reexamination Certificate

active

06744667

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a bit line control decoder circuit, a virtual ground type nonvolatile semiconductor storage device provided with the decoder circuit, and a data read method of the virtual ground type nonvolatile semiconductor storage device.
In recent years, flash memory capacity is being increased according to the functional development of portable telephones and the expansion of uses on the market of memory cards and files, and devices of small effective cell areas, such as a multi-valued system and a virtual ground array system have successively been developed in order to cope with cost reduction. In particular, the virtual ground array system, which can achieve a small cell area by devising a circuit thereof, permits the development of a device of a small chip area through the same processes. However, because of the virtual ground structure, there cannot be ignored a leak current (properly referred to generically as a “leak current to the adjacent cell”) from the memory cell subjected to read (this is referred to as a “read cell”) to the cell (this is referred to as an “adjacent cell”) located adjacent to the cell or from the adjacent cell to the read cell, and various devices are needed to achieve high-speed read.
In order to improve the aforementioned problem, Japanese Patent Laid-Open Publication Nos. HEI 3-176895 and HEI 6-68683 propose virtual ground array read methods.
FIG. 10
shows the construction of the virtual ground type memory array of an EPROM disclosed in Japanese Patent Laid-Open Publication No. HEI 3-176895. A memory cell
10
is constructed of the well-known electrically programmable insulated gate n-channel field-effect transistor. Each memory cell
10
has a control gate connected to a row line
15
, a source region connected to a source column line
12
and a corresponding drain region connected to a drain column line
13
. In this figure, the source column line
12
and the drain column line
13
are buried bit lines formed of a diffusion region.
When a memory cell
10
b
is selected from this memory array to read the contents, the selection is performed by boosting a row line
15
a
to a positive high potential and concurrently grounding a source column line
12
b
via a transistor
18
. The other drain column lines
13
b
and so on located on the right-hand side of the source column line
12
b
remain floating. A read drain bias potential (DRB) supplied to a circuit point
19
is applied via a transistor
17
to a drain column line
13
a
. A drain bias voltage (RDP) supplied to a circuit point
22
is applied via a transistor
20
to a source column line
12
a
connected to an adjacent cell
10
a
. The other source column lines
12
and so on located on the left-hand side of the source column line
12
a
remain floating.
The value of the read drain bias potential RDP supplied to the circuit point
22
is equal to the potential DRB supplied to the circuit point
19
, both being, for example, 1.2 [V]. By supplying the same voltage, a read current wholly flows through the read cell
10
b
without branching into the adjacent cell
10
a
. By thus preventing the leak current to the adjacent cell, high-speed access is achieved.
FIG. 11
shows the construction of a virtual ground type memory array disclosed in Japanese Patent Laid-Open Publication No. HEI 6-68683. In this memory array, diffusion wiring lines
1
through
9
operate as diffusion virtual ground lines and diffusion bit lines arranged alternately. The gate wiring lines
10
,
11
,
12
,
13
,
20
and so on are formed in a direction perpendicular to the diffusion wiring lines
1
through
9
. A metal bit line
30
is provided every two diffusion bit lines, and bit line selecting NMOS transistors
103
and
104
are provided for the connection of the lines. Moreover, one metal virtual ground line is provided every two adjoining diffusion virtual ground lines, and diffusion virtual ground line selecting transistors
51
,
52
,
53
,
61
,
62
and
63
are provided for the connection of the lines. In addition, precharge select circuits
70
and
71
are provided.
When a memory cell
101
is selected from this memory array to read the contents, the diffusion virtual ground line select line
12
and the diffusion bit line select line
10
are first pulled up to Vcc simultaneously with the word line, and the diffusion virtual ground line select line
13
and the diffusion bit line select line
11
are made to have the ground level. At this time, only the metal virtual ground line
201
is pulled down to the ground level, and all the other metal virtual ground lines are made to have a precharge level Vpc. Consequently, the diffusion virtual ground lines
6
and
7
come to have the ground level, and the other diffusion virtual ground lines
5
,
8
and
9
come to have the Vpc level. Moreover, with regard to the metal bit lines, a metal bit line
302
is selected by a Y-gate
24
. Then, a select signal BSR of the diffusion bit line select line
10
is set at the Vcc level, and a select signal BSL of the diffusion bit line select line
11
is set at the ground level, therefore bringing about a state in which the diffusion bit line
3
is selected. Consequently, the diffusion virtual ground line
8
of the adjacent cell
102
is precharged with Vpc. In the above-mentioned manner, the leak current from the diffusion bit line
3
of the read cell to the adjacent cell
102
is suppressed.
In order to further increase the integration density, the virtual ground type memory array is constructed so that an identical diffusion bit line of one block is connected to the largest possible amount of memory cells. Moreover, in order to increase the capacity of the block select transistor to increase the reading speed, there is adopted a method for connecting the diffusion bit lines to the select transistors alternately into different directions every bit line for the provision of transistors of the largest possible size. In the above-mentioned array construction, the diffusion bit line resistance largely varies depending on the location in the array, and the drain voltage during read also causes a voltage drop depending on the location in the array.
FIG. 6
shows an example in which the drain of the read cell is located farthest from the block select transistor. Assuming that a memory cell MCn
4
enclosed by a circle is the read cell, then a voltage Vread is applied to a bit line MBL
4
connected to the drain. Moreover, a voltage Vdb equal to Vread is applied to a bit line MBL
3
connected to the drain of an adjacent cell MCn
3
in order to prevent the leak current. In this case, the read cell MCn
4
is located farthest from the block select transistor TB
4
, and therefore, the bit line voltage Vread causes a voltage drop due to a bit line resistance Rd. However, the adjacent cell MCn
3
is located nearest to the block select transistor TB
3
, and therefore, the bit line voltage Vdb is supplied to the drain of the adjacent cell MCn
3
without causing a voltage drop. As a result, there is substantially achieved a relation of Vdb>Vread. Therefore, current inflow from the bit line of the adjacent cell MCn
3
occurs when the adjacent cell MCn
3
is in the ON-state, causing a current reduction at the read node. In the worst case, even when the read cell MCn
4
is in the ON-state, there occurs misread that the cell is determined to be in the OFF-state.
As described above, in the conventional system, a voltage difference still occurs between the drain voltage of the read cell and the drain voltage of the adjacent cell, as a consequence of which a leak current flows into the read node depending on the state of the adjacent cell or a current flows from the read node to the adjacent cell. This possibly causes misread. Moreover, there is a problem that high-speed read is prevented by the leak current toward the adjacent cell even before the occurrence of misread.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide a virtual ground type n

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