Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-09-07
2001-08-14
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S051000
Reexamination Certificate
active
06275413
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and, more particularly, to an architecture of an electrically erasable programmable non-volatile memory, especially a EEPROM or a flash EPROM.
BACKGROUND OF THE INVENTION
EPROMS are memories well known to those skilled in the art. Each cell includes at least one floating-gate transistor and one access transistor. According to the usual matrix architecture of memories, each cell is controlled by a bit line and a word line of the memory. Each cell can thus be read or written individually by the selection of the corresponding bit line and word line.
It is also common practice to provide for a word access to the memory. Many data elements in applications are encoded not on one bit alone, but on several bits. The common memory architectures thus provide for the possibility of simultaneously accessing several bits, typically 8, 16 or 32 bits. In all cases, the basic unit in terms of a memory word is the byte, formed by eight bits. Most memory architectures are based on the byte.
In practice, the eight bits of a byte are located on the same word line. In the case of a 16-bit memory, the memory array is generally divided into two. A 16-bit word is formed by one byte in one half-array and by another byte in the other half-array. Because of the large memory capacities that are being sought, a word line provides access to several bytes. For example, it is possible to have 128 bit lines for 128 word lines. Each word line thus contains 16 bytes.
To simultaneously select all the bits of a word of a word line, there is a provision for grouping the words of the memory into columns. The i ranking column is the one that comprises the word of the same rank in each word line. An architecture of this kind calls for additional access transistors, each making it possible to select a particular column of the memory. Depending on the specifications of the memory access operations, there are various architectures available to the designer.
One example of a memory architecture organized in word columns of n memory cells is shown in FIG.
1
. This architecture provides one additional access transistor per word of the memory. If the memory has p word lines and N columns, there are p access transistors per column, i.e., one per word line, this gives a total of pxN additional access transistors, i.e., one per word. These additional access transistors receive a signal for the selection of the associated word line as well as a signal for the selection of the associated column. These signals are given by the address decoding circuit of the memory.
FIG. 1
shows a memory organized in word columns of n=8, memory cells C
0
to C
7
comprising p word lines W
1
0
to W
1
p−1
, and N columns Col
0
to Col
N−1
. Each column has eight bit lines B
0
to B
7
, each connected to the same ranking cells of the words of the column.
Each memory cell has an access transistor Ta series-connected with a floating-gate transistor Tf. The access transistor Ta is connected at its gate to the corresponding word line and at its drain to the corresponding bit line. An additional column access transistor is planned per word. This column access transistor, for example, Tc
0,0
, is connected at its gate to the corresponding word line W
1
0
and at its drain to the corresponding column selection line Col
0
. At its source, it transmits a word selection line Sel
0,0
, applied to the control gate of the floating-gate transistors of the cells C
0
to C
7
of the word considered.
Typical EEPROM memory architectures comprise source lines to draw the sources of the memory cells to ground, especially for reading. In the case of a word access memory architecture, one line source per column is provided. The source line LS
0
for the column Col
0
connects the sources of the floating-gate transistor of the memory cells of this column to a corresponding ground connection transistor MS
0
.
Referring again to
FIG. 1
, there are N source lines LS
0
to LS
N−1
and N ground connection transistors MS
0
to MS
N−1
, i.e., one per column. The number of these transistors depends typically on the memory architecture chosen by the designer, application constraints, and the design and drawing rules. It is thus possible to have a single ground connection transistor for the entire memory array, provided that it can let through all the current needed into the different access modes of the memory.
A problem that arises with the word access memory architectures is in the connection of the sources of the floating-gate transistors of the memory cells to a ground connection transistor that is outside the memory array. The sources of the memory cells are diffusions. The connection of these diffusions to a ground connection transistor must take account of the layout constraints related to the technology, and must use as little layout space as possible.
The aim is to obtain a small-sized and low cost finished product. One metal source line per column is typically used to connect the diffusion of the sources of the memory cells to the ground connection transistor. This source line must be located outside the layout zones of the memory cells so as not to add an additional metal layer level in the integrated circuit.
FIG. 2
a
shows the partial layout of the first two words of two consecutive word lines WL
1
and WL
2
. This layout shows the making of one diffusion zone for each word. In the first column Col
0
of the memory, the diffusion zone LD
1,0
forms the source s
0
, . . . , S
7
of each of the floating-gate transistors of the memory cells C
0
to C
7
of the first word of the word line W
1
1
. The diffusion zone LD
2,0
forms the source s
0
, . . . , s
7
of each of the floating-gate transistors of the memory cells C
0
to C
7
of the first word of the word line W
1
2
.
In the second column Col
1
of the memory, the diffusion zone LD
1,1
forms the source s
0
, . . . , s
7
of each of the floating-gate transistors of the memory cells C
0
to C
7
of the second word of the word line Wl
1
. The diffusion zone LD
2,1
forms the source s
0
, . . . , S
7
of each of the floating-gate transistors of the memory cells C
0
to C
7
of the second word of the word line W
1
2
.
Each of these diffusion zones thus forms a diffusion line in a direction perpendicular to the sources. Each diffusion line is formed to a respective contact used to connect it to a metal source line of the associated, perpendicular column. The contact and the source line are made outside the layout zone of the memory cells of the column considered. In the example, for diffusion lines LD
1,0
and LD
2,0
, there correspond respectively the contacts P
1
, P
2
on the metal source line LS
0
of the column Col
0
. To the diffusion line LD
1,1
and LD
2,1
, there respectively correspond the contacts P
3
, P
4
on the metal source line LS
1
of the column Col
1
.
According to this layout, two successive columns are separated from each other by a metal source line. With a layout of this kind, there is a loss of current in the connection path of the sources at the ground connection transistor. The diffusion zones are resistive, and induce a considerable loss of current as a function of length. The amount of this loss of current varies for each cell within the same word.
Referring again to
FIG. 2
a
, the cell C
7
of a word is connected to the source line by a smaller diffusion length than is the cell C
0
of the same word. Thus, the loss of current in the cell C
7
is smaller than in the cell C
0
. In other words, the loss of current in a cell of a word, due to the diffusion length for connecting the source of this cell of a word to the corresponding source line, is a function of its rank in this word.
This loss of current is very troublesome, especially in the word read access mode. It may be recalled that the EEPROM memory cells, which are blank when they come off the production line, can then be electrically programmed. This lowers the threshold voltage of their floating-gate transistor. Alternativel
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Fears Terrell W.
Galanthay Theodore E.
STMicroelectronics S.A.
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