Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-04-26
2001-04-24
Nelms, David (Department: 2810)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330
Reexamination Certificate
active
06222768
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of flash memory devices. More particularly, the invention relates to a method for auto adjusting window placement for an NROM virtual ground array.
BACKGROUND OF THE INVENTION
The overall array architecture for a typical virtual ground array based flash memory device includes a virtual ground array accessed by a set of row decoders and a set of column decoders/multiplexors. The virtual ground array contains information stored in individual memory elements. The row/word-line decoders are used to access specific memory rows within each memory block and the column decoder/multiplexor provides the input and output circuitry for each memory element.
The architecture of a virtual ground array comprises both individual memory elements and select gates. The memory elements are embodied in non-volatile transistors that may be programmed to a logic state of 0, 1, or other states depending on the particular type of transistor and programming used. The select gates are embodied in normal MOSFETs. Selectable word lines address both the control gates of the transistors that comprise the individual memory elements and select gates in the virtual ground array. Sets of memory elements are connected in series along each word line. The select gates are connected in pairs that are coupled to alternate select gate address lines. The pairs of select gates are connected with pairs of memory elements and a global bitline. Multiplexors control the columns that are connected to the external circuitry, such as the sensing circuitry and data-in path. The multiplexors are controlled by a set of column address decoders. Thus, the decoders and multiplexors regulate the flow of data into and out of the virtual ground array.
Variations of the threshold voltage of the individual memory elements within the virtual memory array occur as a result of continual erasing and programming over time of the memory device. After an erase/program operation on memory elements in the array it is necessary to verify that the memory elements have been erased or programmed to the correct level. The levels may be determined by using a safe and accurate sensing scheme that senses from the source rather than the drain side of the virtual ground array. Using the drain side has a number of disadvantages. The main disadvantage of drain side sensing is that all the other bitlines connected with memory elements on the drain side not being sensed must be precharged to the drain voltage or higher before the sensing routine commences. Precharging the bitlines, in this case, wastes both time and power. Time is necessary to initiate, perform, and verify the precharging sequence when sensing from the drain side. Excess power is consumed in each of the precharge steps as well, for example decreasing battery lifetime for any portable electronics unit using the virtual ground array. In addition, sensing from the drain side leads to larger leakage currents and more thus error. Further, once it has been determined that the levels have deviated significantly from previous values necessary for normal operation, the window of operating voltages must be altered to decrease any errors obtained during normal operations due to the change.
BRIEF SUMMARY OF THE INVENTION
In view of the above, a method for automatically adjusting the placement of a window of threshold voltages for verification during operation in a virtual ground array is provided.
A first aspect of the invention is directed to a method of automatically adjusting the placement of the window. The method comprises selecting a set of memory elements contained in the virtual ground array. The selected memory elements may be erased or programmed. The placement of a window of operating voltages is adjusted in response to the source current from a selected memory element in the set. The window of operating voltages has a range of operating voltages containing, in order of increasing voltage, an erase voltage, a read voltage, and a program voltage of the selected memory element. The verification and adjustment occurs for each memory element in the set of memory elements.
The source current may be determined by transforming the source current into a sense voltage via a sense transforming means. In addition, a reference current must then be transformed into a reference voltage via a reference transforming means, and the sense voltage and reference voltage comparing via a comparator. The reference current originates from one of set of reference sources. Either (or both) transforming means may be controlled and may be comprised of capacitors, resistors, or transistors.
The adjustment may be accomplished by a number of acts. These acts may include verifying that the selected memory element was erased to a sufficient erase voltage and determining the number of verifications when the selected memory element was not erased to the sufficient erase voltage. When the number of verifications is smaller than a predetermined amount, the selected memory element is properly erased. When the number of verifications is larger than the predetermined amount of verifications, the number of programmings applied to the reference source is determined. When the number of programmings is smaller than the number needed to achieve the maximum amount of adjustment the set of reference sources is programmed by an incremental amount thus establishing a new set of operation thresholds. This is repeated until either the source current is approximately equal to the reference current or failure occurs. Failure of at least the selected memory element is indicated when the number of programmings is greater than number necessary to effect the maximum amount of adjustment.
In addition, the number of verifications may be counted by a pulse counter which is incremented prior to repeating the verification. The pulse counter is reset after the maximum number of verifications is determined. The number of programmings to the set of reference sources may be counted by referring to a set of registers. The set of registers is incremented anytime after the determination of the number of programmings and prior to repeating the verification.
It is therefore a primary advantage of the present invention to increase the reliability and functionality of the virtual ground array by characterizing at least a portion of the threshold voltages of the memory elements in the virtual ground array and subsequently adjusting operation voltages accordingly.
The following figures and detailed description of the preferred embodiments will more clearly demonstrate these and other objects and advantages of the invention.
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Chen Pau-Ling
Hollmer Shane
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Lam David
Nelms David
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