Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-09-06
2004-09-28
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S236000
Reexamination Certificate
active
06798695
ABSTRACT:
The invention relates to an arrangement for storing a count with a non-volatile memory.
Arrangements are provided, for example, for access systems, which arrangements re-store a count of a counter after each counting operation. Since such systems can be used under critical by-pass conditions, great importance is to be placed on an error-free storage of the count in a non-volatile memory (for example in an EEPROM). Such interruptions may occur in the power supply itself, for example, by a failure of the battery voltage, but it may also be an insufficient contact or a switch-over of the operating voltage.
Known memory arrangements provided for such purposes work with a redundant storage of each new count. This means that the new count is stored in two or even three memory segments of an EEPROM and there is established by validity flags, by checksum tests or by comparison of the memory contents which count is valid.
These known arrangements have the disadvantage that the EEPROM with each storage of a new count is to be written anew into two memory segments and thus the useful life of the EEPROM which permits only a limited number of storing cycles is unnecessarily shortened.
It is an object of the invention to provide an arrangement of the type defined in the opening paragraph which writes only one memory segment for each storage of a new count even under the secured conditions mentioned in the introductory part.
If a new count is written in a non-volatile memory after a counting operation in the arrangement, disturbances in the voltage supply may occur during this operation so that, where appropriate, the stored value is false or can no longer be read. As the case may be, the externally provided counter may also have a memory but the contents of the memory may be erased as a result of failures of the power supply. As a result, the latest count can no longer be reconstructed in such a case.
The arrangement according to the invention is therefore to satisfy two conditions. On the one hand, it should be possible to establish which count is invalid, thus, for example, developed from writing during a power failure and having an arbitrary value but not corresponding to the count to be stored. After identification of such a “falsely” stored count, the latest valid count stored before this invalid count is to be found.
The arrangement according to the invention stores each new count only in one of the three memory segments of a non-volatile memory. As against the state-of-the-art arrangement a doubling or tripling, respectively, of the useful life of the EEPROM is thus achieved.
In order to achieve this object a controller provided in the arrangement selects before it stores a new count in one of the memory segments the segment that either has an erroneous count or is selected in accordance with a selection instruction which is oriented to memory contents.
For the selection of this memory segment the controller searches for a memory segment whose stored value has the largest difference compared to the stored values of the other memory segments. Thus for each of the memory segments its stored value is compared to the stored values of the other memory segments and, accordingly, differences are formed. If a stored value of one of the memory segments has a larger difference from the stored values of the other memory segments than the stored values of the other memory segments, it is selected for the write operation.
The largest difference is an indication that it is an erroneously stored count because when the counts are stored correctly the sums of the differences of the stored values of a memory segment are to equal the stored values of the other memory segments. This means that for each memory segment this sum is to be equal to the difference. However, if a count has been stored erroneously in one of the memory segments, this difference is most probably larger. Therefore, the stored value of this memory segment is an erroneously stored count. This memory segment thus found is selected for storing the new count because it has invalid contents.
If no memory segment is found whose stored value has a larger difference from the stored values of the other memory segments than the stored values of the other memory segments, a memory segment is selected oriented to the memory contents.
This is the normal case where the stored values of all three memory segments are valid and thus have the same differences from the other stored values. In this case the new memory segment to be written is selected according to a selection instruction in dependence on the memory contents. This selection instruction may depend, for example, on the type of the counting operation; in dependence on the counting rate the memory segment is selected on the basis of which the counting operation is to be continued.
The arrangement according to the invention thus avoids any redundant storage and nevertheless achieves the advantage that even in the case of failures of the power supply and invalid memory contents of a memory segment the counting rate is not disturbed, because the memory segment that detects invalid contents is written anew and thus, thereafter, valid counts are stored in all three memory segments from which counts further counting operations may be proceeded with.
The circuitry and cost involved in the implementation is relatively low and besides, the method generally leads to an increase of the security against data loss. Since the memory segments are exclusively used for storing counts, these operations may be optimized and thus an increase of the permitted number of write cycles can be achieved.
An embodiment of the invention as claimed in claim
2
provides for the case where the external counter is an up-counter that the selection instruction consists of selecting the memory segment that has the lowest stored value. In the case where no memory segment is found whose stored value has higher differences from the stored values of the other memory segments than the stored values of the other memory segments, the selection instruction takes effect which, in an up-counter may advantageously consist of selecting for the new storage operation the memory segment that has the lowest stored value because this memory segment contains the oldest count.
Conversely, as provided in accordance with a further embodiment of the invention as claimed in claim
3
, the memory segment having the highest stored value can be written anew if a down-counter is provided.
As claimed in claim
4
a threshold may be advantageously provided for determining the differences described above, at the exceeding of which threshold it is assumed that the respective memory segment contains an invalid stored value. With the known counting rate it is also known what maximum differences the stored values of the memory segments may have compared to each other. If for a stored value of a memory segment there are higher differences which transgress the threshold, it may be assumed that this stored value is invalid. Therefore, already when the threshold is transgressed, the above requirement may be considered satisfied so that in the case where this threshold is transgressed during the difference formation, the respective memory segment is immediately selected for storing the new count.
According to further embodiments of the invention as claimed in claims 5 and 6 there is provided that a new count to be calculated starting from the maximum stored value of the memory segments in case of an up-counter and from the minimum stored value of the memory segments in case of a down-counter.
The externally provided counter may thus advantageously select this value from the memory segments and use it for the next counting operation.
An example of embodiment of the arrangement according to the invention for storing counts will be further explained with reference to the sole FIGURE of the drawing.
REFERENCES:
patent: 4150333 (1979-04-01), Edwards et al.
patent: 4774544 (1988-09-01), Tsuchiya et al.
Boeh Frank
Nowottnick Juergen
Koninklijke Philips Electronics , N.V.
Le Thong Q.
Waxler Aaron
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