Array and pitch of non-volatile memory cells

Details Array and pitch of non-volatile memory cells Array and pitch of non-volatile memory cells

2009-01-29

2010-11-23

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185020, C365S185110, C365S185230

Reexamination Certificate

active

07839682

ABSTRACT:
An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.

REFERENCES:
patent: 5270979 (1993-12-01), Harari et al.
patent: 5761119 (1998-06-01), Asano
patent: 7567458 (2009-07-01), Tran et al.

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