Bit line biasing method to eliminate program disturbance in a no

Details Bit line biasing method to eliminate program disturbance in a no Bit line biasing method to eliminate program disturbance in a no

1998-10-20

1999-11-02

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518523, G11C 1604, G11C 1606

Patent

active

059782676

ABSTRACT:
In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

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