Bit line gate transistor structure for a multilevel,...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185290, C365S185330

Reexamination Certificate

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07830713

ABSTRACT:
A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the serially connected select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected select transistor. The pair of serially connected top select transistors is connected to a first of two associated bit lines. Optionally, the NAND nonvolatile memory strings further is connected a pair of serially connected bottom select transistors that is connected to the second associated bit line.

REFERENCES:
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5812454 (1998-09-01), Choi
patent: 6163048 (2000-12-01), Hirose et al.
patent: 6490204 (2002-12-01), Bloom et al.
patent: 6614070 (2003-09-01), Hirose et al.
patent: 6614692 (2003-09-01), Eliyahu et al.
patent: 6845042 (2005-01-01), Ichige et al.
patent: 6937521 (2005-08-01), Avni et al.
patent: 7113431 (2006-09-01), Hamilton et al.
patent: 7116577 (2006-10-01), Eitan
patent: 7120063 (2006-10-01), Liu et al.
patent: 7123532 (2006-10-01), Lusky et al.
patent: 7136304 (2006-11-01), Cohen et al.
patent: 7151293 (2006-12-01), Shiraiwa et al.
patent: 7158411 (2007-01-01), Yeh et al.
patent: 7170785 (2007-01-01), Yeh
patent: 7187030 (2007-03-01), Chae et al.
patent: 7203092 (2007-04-01), Nazarian
patent: 2006/0171209 (2006-08-01), Sim et al.
patent: 2006/0180847 (2006-08-01), Park et al.
patent: 2006/0245233 (2006-11-01), Mikolajick et al.
patent: 2007/0115723 (2007-05-01), Chen et al.
patent: PCT/US2008/003400 (2008-05-01), None
Co-pending US Patent AP07-001, U.S. Appl. No. 60/903,731, filed Feb. 26, 2007, “Circuits and Algorithms for Simultaneous Programming and Reading Multiple-Level, Dual-Sided Cell in NAND, NOR, EEPROM and Combo Flash Arrays,” assigned to the same assignee as the present invention.
Co-pending US Patent AP07-002, U.S. Appl. No. 60/904,294, filed Feb. 28, 2007, “Circuits and Algorithms for Simultaneous Programming and Reading the Single-Poly, Multiple-Level, Dual-Sided Cell in NAND, NOR, EEPROM and Combo Flash Arrays,” assigned to the same assignee as the present invention.
Co-pending US Patent AP07-001, U.S. Appl. No. 12/069,637, filed Feb. 12, 2008, “A Circuit and Method for Multiple-Level Programming, Reading, and Erasing Dual-Sided Nonvilatile Memory Cell,” assigned to the same assignee as the present invention.
Co-pending US Patent AP07-002, U.S. Appl. No. 12/069,228, filed Feb. 8, 2008, “A Bit Line Structure for a Multilevel, Dual-Sided Nonvolatile Memory Cell Array,” assigned to the same assignee as the present invention.
“Intel StrataFlash™ Memory Technology Overview,” By Atwood et al., Intel Technology Journal Q4'97, pp. 1-8.
“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” by Eitan et al., IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
“A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes,” by Cho et al., IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp. 1700-1706.
“A 146-mm squared 8-Gb Multi-Level NAND Flash Memory with 70-nm CMOS Technology,” by Hara et al., IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, pp. 161-169.

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