Array VSS biasing for NAND array programming reliability

Details Array VSS biasing for NAND array programming reliability Array VSS biasing for NAND array programming reliability

1998-02-17

1999-11-02

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518502, 36518528, G11C 1604

Patent

active

059782668

ABSTRACT:
A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.

REFERENCES:
patent: 5204839 (1993-04-01), Lee et al.

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