Array-source line, bitline and wordline sequence in flash operat

Details Array-source line, bitline and wordline sequence in flash operat Array-source line, bitline and wordline sequence in flash operat

1995-11-20

1997-08-12

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518511, 36518512, 36518502, G11C 700

Patent

active

056572689

ABSTRACT:
In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector. An erasing method includes connecting the wordlines to a reference voltage, connecting at least one deselected common array-source line to each bitline coupled to drains of columns of memory cells in the deselected sector, then biasing at a positive voltage both the deselected common array-source line and said bitlines coupled to drains of memory cells in columns of the deselected sector, and then applying a positive erasing voltage to said common array-source line of the selected sector.

REFERENCES:
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5185718 (1993-02-01), Rinerson et al.
patent: 5384742 (1995-01-01), Miyakawa et al.

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