Latch circuit and synchronous memory including the same
Latched type clock synchronizer with additional 180.degree.-phas
Late-write type SRAM in which address-decoding time for reading
Latency control circuit and method of latency control
Latency control circuit and method of latency control
Latency control circuit and method of latency control
Latency control circuit and method of latency control
Latency control circuit and method thereof and an...
Latency counter
Latency counter, semiconductor memory device including the...
Latency counter, semiconductor memory device including the...
Latency normalization by balancing early and late clocks
Latency time circuit for an S-DRAM
Latency time switch for an S-DRAM
Lead frame clock distribution for integrated circuit memory devi
Line memory for speed conversion
Load signal generating circuit of a packet command driving...
Localized ATD summation for a memory
Logic and memory circuit with reduced input-to-output signal pro
Loop filtering for fast PLL locking