Late-write type SRAM in which address-decoding time for reading

Details Late-write type SRAM in which address-decoding time for reading Late-write type SRAM in which address-decoding time for reading

1996-08-30

1998-02-10

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518907, 36523006, G11C 800

Patent

active

057176531

ABSTRACT:
A static random-access memory (SRAM) of late-write type, in which the total time required to write data is reduced, thereby increasing the write margin. No time is therefore wasted in writing and reading data. The SRAM has an address register for holding a write address, besides an address register for holding an input address. A pass gate selects the write address held in the address register or the input address held in the address register. In a read cycle, a decoding path is formed to decode a read address, without using delay circuits. In a write cycle, a second decoding path is formed to decode a write address, using delay circuits. In the cycle preceding the first write cycle coming after the operating mode of the SRAM is switched from the read mode to the write mode, a third decoding path is formed to decode the write-address signal read from the address register. The first, second and third decoding paths are controlled by pass gates.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.

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