Latency counter, semiconductor memory device including the...

Details Latency counter, semiconductor memory device including the... Latency counter, semiconductor memory device including the...

2008-07-09

2010-11-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S236000

Reexamination Certificate

active

07826305

ABSTRACT:
A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.

REFERENCES:
patent: 5999458 (1999-12-01), Nishimura et al.
patent: 7345950 (2008-03-01), Fujisawa et al.
patent: 2006/0250883 (2006-11-01), Szczypinski
patent: 2008/0043566 (2008-02-01), Fujisawa
patent: 2008/0192563 (2008-08-01), Cho
Song Ho Young., et al., “A 1.2Gb/s/pin Double Data Rate SDRAM with On-Die-Termination”, ISSCC 2003/Session 17/SRAM and DRAM/PAPER 17.8, IEEE, 2003, p. 314.

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