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Packaged integrated circuit synchronous memory device with...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Parallel asynchronous propagation pipeline structure and...

Static information storage and retrieval – Addressing – Sync/clocking
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Parallel asynchronous propagation pipeline structure to...

Static information storage and retrieval – Addressing – Sync/clocking
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Parallel data path architecture

Static information storage and retrieval – Addressing – Sync/clocking
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Peripheral buses for integrated circuit

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Phase comparator with improved comparison precision and synchron

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Phase control circuit, semiconductor device and...

Static information storage and retrieval – Addressing – Sync/clocking
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Phase control circuit, semiconductor device and...

Static information storage and retrieval – Addressing – Sync/clocking
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Phase controlled high speed interfaces

Static information storage and retrieval – Addressing – Sync/clocking
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Phase locked loop circuit and method of locking a phase

Static information storage and retrieval – Addressing – Sync/clocking
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Phase locked loop circuit and method of locking a phase

Static information storage and retrieval – Addressing – Sync/clocking
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Phase shift correction circuit for monolithic random access memo

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Phase-locked loop timing controller in an integrated circuit mem

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pipelined chip enable control circuitry and methodology

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pipelined chip enable control circuitry and methodology

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pipelined dual port RAM

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Pipelined read architecture for memory

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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PLL circuit for increasing potential difference between...

Static information storage and retrieval – Addressing – Sync/clocking
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Power saving synchronization circuit and semiconductor storage d

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Power savings for memory arrays

Static information storage and retrieval – Addressing – Sync/clocking
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