Latency control circuit and method of latency control

Details Latency control circuit and method of latency control Latency control circuit and method of latency control

2002-10-30

2004-03-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000

Reexamination Certificate

active

06707759

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. 1
illustrates a block diagram of a prior art memory device. The memory device
100
includes a memory cell array
110
, a clock synchronizing circuit block
120
, a read command path block
130
, a data output buffer
140
, a mode register
150
and a latency circuit
160
. In operation, data is written into the memory cell array
110
and read out from the memory cell array
110
. If a read command is asserted to the memory device
100
, data is read out from the memory cell array
110
according to an externally received address. A buffer
116
receives and temporarily stores the address. A row decoder
112
receives the stored address and decodes a row address of the memory cell array
110
from the address. A column decoder
114
receives the stored address and decodes a column address of the memory cell array
110
from the address. The memory cell array
110
outputs the data addressed by the row and column addresses. The data output buffer
140
receives the data output from the memory cell array
110
, and outputs the data based on a latency signal from the latency circuit
160
and an internal data output clock signal CLKDQ.
The clock synchronizing circuit block
120
generates the data output clock signal CLKDQ based on an external clock signal ECLK. The external clock signal ECLK serves as a reference clock signal for most commands of the memory device
100
. Specifically, most commands are asserted to the memory device
100
in synchronization with the external clock signal ECLK. As shown in
FIG. 1
, the clock synchronizing circuit block
120
is a delay locked loop (DLL) circuit. The DLL circuit
120
includes a variable delay
122
, a data output buffer replica
124
and a phase detector
126
. The DLL circuit
120
is a well known circuit such as described in U.S. Pat. No. 5,614,855; and therefore, will not be described in detail. The DLL circuit
120
generates the data output clock signal CLKDQ as a phase lead version of the external clock ECLK. Namely, the data output clock signal CLKDQ has the same frequency as the external clock ECLK, but the pulses of the data output clock signal CLKDQ precede the pulses of the external clock signal ECLK by a data output time tSAC. The data output time is a measurement of the time it takes the data output buffer
140
to output data. Accordingly, the DLL circuit
120
causes data to be output from the data output buffer
140
in synchronization with the external clock ECLK.
The read command path block
130
receives the read command and the external clock signal ECLK. An internal clock generator
132
receives the external clock signal ECLK and generates an internal clock signal PCLK from the external clock signal ECLK. Specifically, the internal clock signal PCLK is a buffered version of the external clock signal ECLK. Therefore, the internal clock signal PCLK has the same frequency as the external clock signal ECLK and the level of the internal clock signal PCLK swing is a CMOS level (VSS-VCC) buffered signal delayed from the external clock signal ECLK. The internal clock signal PCLK is used to control peripheral circuits (not shown) such as data sense amplifiers, data multiplexers, etc., in the memory device
100
. A read command buffer
134
in the read command path block
130
receives the read command and the internal clock signal PCLK. The read command buffer
134
inputs the read command synchronized with the internal clock signal PCLK, and outputs an internal read signal PREAD, which is supplied to the latency circuit
160
.
The memory device
100
has several modes of operation. The mode register
150
stores a mode register set (MRS) command asserted to the memory device
100
. The MRS command indicates the mode of the memory device
100
. A CAS latency CLi (where i is a natural number) is determined by the MRS command. The CAS latency indicates the number of clock cycles of the external clock signal ECLK that should occur between the receipt of a read command or column address until data is output by the memory device
100
. Stated another way, data is output from the memory device in a CAS latency number of clock cycles after receipt of the read command (a column address being asserted together with the read command).
The latency circuit
160
receives the CAS latency from the mode register
150
and generates a latency signal such that the data output buffer
140
is enabled to output the data according to the desired CAS latency. More specifically, the data output buffer
140
outputs the stored data in response to the data output clock signal CLKDQ while the latency signal is enabled.
FIG. 2
illustrates a prior art latency circuit
160
. As shown, the latency circuit
160
includes first, second and third D-flip flops
215
,
225
and
235
connected in cascade. Each D-flip flop receives the data output clock signal CLKDQ at its clock input. The internal read signal PREAD is supplied to the D input of the first D-flip flop
215
. The internal read signal PREAD and Q output of each of the first-third D-flip flops
215
,
225
and
235
are respectively connected to first-fourth switches
210
,
220
,
230
and
240
. The first-fourth switches
210
,
220
,
230
and
240
are respectively controlled by a CAS latency CL
1
, CL
2
, CL
3
and CL
4
, and the output of the first-fourth switches
210
,
220
,
230
and
240
serve as the latency signal. In operation, only one of the CAS latency modes will be logic high; therefore, only one of the first-fourth switches
210
,
220
,
230
and
240
will transfer a signal for output as the latency signal. For example, when the CAS latency is
1
, CL
1
is logic high and turns on first switch
210
. At this time, CAS latencies CL
2
, CL
3
, and CL
4
are logic low. The internal read signal is then transferred as the latency signal via the first switch
210
. When the CAS latency is two (i.e., CL equals 2), then CL
2
is logic high, while CL
1
, CL
3
and CL
4
are logic low. Thus, the internal read signal PREAD is transferred as the latency signal via the first D-flip flop
215
and the second switch
220
. The first D-flip flop
215
is triggered by the data output clock signal CLKDQ and delays the internal read signal PREAD being output as the latency signal by about one clock cycle. The operation when the CAS latency is three or four is similar to that discussed above with respect to the CAS latency of two, and therefore will not be repeated for the sake of brevity. Additionally, it will be understood that CAS latencies greater than four could be handled by the addition of more D-flip flops and switches.
FIG. 3A
illustrates a timing diagram of the read operation when the CAS latency is 1. At a clock cycle C
0
, a read command
310
is asserted, and an internal read signal PREAD is generated by the read command path block
130
after an internal delay time tREAD. The latency signal is then enabled in response to the internal read signal PREAD as discussed above with respect to FIG.
2
. As further shown in
FIG. 3A
, the DLL circuit
120
generates the data output clock signal CLKDQ such that the rising edge of the data output clock signal CLKDQ precedes the rising edge of the external clock signal ECLK by a period of time tSAC, where the time period tSAC equals the delay between enabling data output from the data output buffer
140
and the actual output of data from the memory device
100
. As further discussed above with respect to
FIG. 1
, the data output buffer
140
outputs data when triggered by the data output clock signal CLKDQ only when the latency signal is enabled. Because the CAS latency has been set to 1 in this example, the latency signal is enabled prior to receipt of the data output clock signal CLKDQ. As a result, data is output from the memory device
100
in synchronization with the first clock pulse C
1
of the external clock signal ECLK following the clock pulse C
0
of the external clock signal ECLK when the read command
310
was received. The time delays tREAD and tSAC are internal delays set according

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