Line memory for speed conversion

Details Line memory for speed conversion Line memory for speed conversion

1989-06-08

1990-07-31

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Sync/clocking

365219, 365221, 365236, 307480, 377 76, G11C 700

Patent

active

049455184

ABSTRACT:
A line memory for speed conversion, whose data rates of write into and read from a memory cell (1) differ from each other, has a write circuit (2, 3, 4) for writing input data (D.sub.in) into the cell (1) at a predetermined rate and resetting the write address of the cell (1) at a predetermined period, a read circuit (5, 6, 7) for reading data (D.sub.out) from cell (1) at a rate different from the write rate and resetting the read address of the cell (1) at the predetermined period, the first shift circuit (8) for shifting reset timing of the write address, and the second shift circuit (9) for shifting reset timing of the read address, the first and second shift circuits enabling respective setting quantities at the same value. This memory can shift both the write address reset timing and the read address reset timing while keeping both in the same condition.

REFERENCES:
patent: 3577086 (1971-05-01), Kliman et al.
patent: 4287577 (1981-09-01), Deal
patent: 4823321 (1989-04-01), Aoyama

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