Latency control circuit and method thereof and an...

Details Latency control circuit and method thereof and an... Latency control circuit and method thereof and an...

2006-11-09

2009-10-27

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C385S105000, C385S046000, C385S046000

Reexamination Certificate

active

07609584

ABSTRACT:
A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

REFERENCES:
patent: 6356494 (2002-03-01), Jang et al.
patent: 6914850 (2005-07-01), Chai
patent: 7085192 (2006-08-01), Fujisawa et al.
patent: 2002/0036947 (2002-03-01), Kouchi et al.
patent: 2004/0233773 (2004-11-01), Shin
patent: 2004/0264275 (2004-12-01), Gou
patent: 2006/0104150 (2006-05-01), Yoshida et al.
patent: 2000-030456 (2000-01-01), None
patent: 2001-148191 (2001-05-01), None
patent: 2002-117672 (2002-04-01), None
patent: 2004-253123 (2004-09-01), None
patent: 1020000011667 (2000-02-01), None
patent: 1020000045402 (2000-07-01), None
patent: 1020010067430 (2001-07-01), None
patent: 1020020015864 (2002-03-01), None
patent: 10-0532421 (2004-08-01), None
patent: 1020040074283 (2004-08-01), None
patent: 1020050003527 (2005-01-01), None
patent: 1020050011954 (2005-01-01), None
German Office Action dated Sep. 3, 2008.

Affiliated with

Also associated with

Rating

Latency control circuit and method thereof and an... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latency control circuit and method thereof and an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latency control circuit and method thereof and an... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4104326