Latency control circuit and method of latency control

Details Latency control circuit and method of latency control Latency control circuit and method of latency control

2005-09-13

2005-09-13

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S194000

Reexamination Certificate

active

06944091

ABSTRACT:
The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

REFERENCES:
patent: 5614855 (1997-03-01), Lee et al.
patent: 6570814 (2003-05-01), Farmwald et al.
patent: 6615307 (2003-09-01), Roohparvar
patent: 6707759 (2004-03-01), Song
patent: 6778465 (2004-08-01), Shin

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