Latency counter

Details Latency counter Latency counter

2007-08-06

2009-12-08

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S236000, C365S189070

Reexamination Certificate

active

07630275

ABSTRACT:
A latency counter includes: a point-shift type FIFO circuit having plural latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and having an internal command MDRDT supplied in common to the input gates; and a selector that makes any one of the input gates and any one of the output gates conductive. The selector includes a counter that changes over between a selection operation of selecting the input gate and a selection operation of selecting the output gate, and the counter outputs a count value in a binary format synchronously with an internal clock ICLK. Because the binary-format counter is used in this way, the count value itself does not cause an error.

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Song et al., “A 1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination,” 2003 IEEE Int'l Solid-State Circuits Conference, Session 17, Paper 17.8 (2003).
Japanese Patent Office issued a Japanese Office Action dated May 12, 2009, Application No. 2006-224575.

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