Logic and memory circuit with reduced input-to-output signal pro

Details Logic and memory circuit with reduced input-to-output signal pro Logic and memory circuit with reduced input-to-output signal pro

1995-04-10

1996-09-17

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365194, 365191, G11C 700

Patent

active

055575811

ABSTRACT:
A logic and memory circuit with reduced input-to-output signal propagation delay includes signal processor and memory elements connected in parallel for performing "memory work" simultaneously with "logical work" and/or "electrical work." Incorporated within a flip-flop having master and slave latches which perform the memory work (i.e. data storage) on the input and output logic signals, respectively, is a signal processor which processes one or more input signals to provide an output signal. Where memory work and electrical work are to be performed simultaneously, the signal processor includes a serial group of circuits having successively larger transistors for buffering an input signal to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively. Where memory work and logical work are to be performed simultaneously, the signal processor includes a logic function circuit (e.g. a logic gate) for logically processing one or more input signals to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively.

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