Scan path circuitry including an output register having a flow t
Scheme for increasing enable access speed in a memory device
SDRAM having data latch circuit for outputting input data in...
SDRAM having posted CAS function of JEDEC standard
SDRAM with a maskable input
Selectable clock input
Selectable clock input
Selective adjustment of voltage controlled oscillator gain...
Selective edge phase mixing
Selective edge phase mixing
Self adjusting sense amplifier clock delay circuit
Self reset clock buffer in memory devices
Self-clocking sense amplifier optimized for input signals close
Self-enabling pulse trapping circuit
Self-enabling pulse-trapping circuit
Self-enabling pulse-trapping circuit
Self-timed sneak current cancellation
Self-timed strobe generator and method for use with...
Semi-conductor component with clock relaying device
Semi-conductor memory component, and a process for operating...