Latency control circuit and method of latency control

Details Latency control circuit and method of latency control Latency control circuit and method of latency control

2006-06-20

2006-06-20

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S193000, C365S230080

Reexamination Certificate

active

07065003

ABSTRACT:
The memory device includes a memory cell array, and an output buffer receiving data addressed from the memory cell array and outputting the data based on a latency signal. A latency circuit selectively associates at least one transfer signal with at least one sampling signal based on CAS latency information to create a desired timing relationship between the associated sampling and transfer signals. The latency circuit stores read information in accordance with at least one of the sampling signals, and generates a latency signal based on the transfer signal associated with the sampling signal used in storing the read information.

REFERENCES:
patent: 6215710 (2001-04-01), Han et al.
patent: 6804165 (2004-10-01), Schrogmeier et al.

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