Load signal generating circuit of a packet command driving...

Details Load signal generating circuit of a packet command driving... Load signal generating circuit of a packet command driving...

2000-06-27

2001-06-12

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

Reexamination Certificate

active

06246636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a load signal generating circuit of a packet command driving type memory device, particularly, to a load signal generating circuit for reading data for generating a load signal for transferring the data read from a core block to an output pad by synchronizing the load signal to a clock signal accurately.
2. Description of the Related Art
FIG. 1
indicates a channel structure in a general packet command driving type memory device, for example, a memory device such as RAMBUS DRAM. Referring to
FIG. 1
, a number of RAMBUS DRAMs are connected respectively on a longbus channel, a phase difference between CTM and CFM is different every RAMBUS DRAM. The more it is distant from a controller, the more the phase difference between CFM and CTM is large. A region that a phase difference increases from a spot of “0” to a spot of “1” is referred to as a latency domain.
In a case of the longbus channel, by that a device of the latency domain being far apart from a controller reads data quickly, that the device of the latency domain being near from a controller reads data slowly, a controller can recognize data in an identical point of time from every device.
FIGS. 2A-2C
show read data according to a prior tdac_en signal and a waveform of a load signal loadRDpipe. Referring to
FIG. 2A
, in a case of tdac_en<3>=1, a signal loadRDpipe has a width of 1 cycle, but referring to
FIG. 2B
, in a case of tdac_en<4>=1, a signal loadRDpipe is delayed by 1 cycle than the case of tdac_en<3>=1. A RAMBUS DRAM can operate not only in 400 MHz (a period of 2.5 ns), but in 300 MHz (a period of 3.3 ns), when tdac_en<4>=1, a hold time t
doh
becomes 2.5 ns (=a width of 1 cycle in 400 MHz) accurately. If it is operated in 300 MHz, a width of read data is as it is, but as a width of a signal loadRDpipe_b is wider, the hold time t
doh
is shortened than 2.5 ns. That is, to maintain t
—doh
=2.5 ns even in 300 MHz, the signal loadRDpipe must become a pulse signal of ½ cycle.
However, in a case that a width of a prior load signal, a signal loadRDpipe has a width of ½ cycle, as a load signal is delayed and outputted through a three stage gate, delayed to the right on the whole as drawn in
FIG. 2
c
, there was a problem that it doesn't satisfy a data hold time specified in spec in an operation of 300 MHz or 400 MHz in this case.
As described above, a hold time specified in spec must be given between data read_data read from a core block and a load signal loadRDpipe_b for loading the read data to an output pad.
FIG. 3
shows a load signal generating circuit for reading data in a prior packet command driving type memory device. Referring to
FIG. 3
, a prior load signal generating circuit for reading data comprises a first inverting gate
21
for inverting a test load signal testLoadRDoioe_b, a first NAND GATE
22
for inputting an output signal of the first inverting gate
21
and a DA test mode signal DAMODE, a first flip flop
23
for receiving an input signal cxff
3
and being synchronized to a clock signal tclk and generating cas_in_ff
4
, a second NAND GATE
24
for receiving the output cas_in_ff
4
of the first flip flop
23
and a signal tdac_en<3>, a first OR GATE
25
for receiving an output signal ldat_dac
3
_b of the second NAND GATE
24
and an inverted signal of ldat_dac
4
_b, a buffer
26
for buffering an output of the first flip flop
23
, a second flip flop
27
for receiving an output signal cxff
4
of the buffer
26
and being synchronized to a clock signal rclk and generating a signal cas_out_ff
4
as an output signal, a second inverting gate
28
for inverting a DA test mode signal DAMODE, a third NAND GATE
29
for receiving an output signal of the second inverting gate
28
and an output signal of the second flip flop
27
cas_out_ff
4
and tdac_en<
4
>, a third flip flop
31
for receiving an output signal cas_out_ff
4
of the second flip flop
27
and generating an output signal x
1
b
by that the clock signal rclk is outputted as an enable signal ENB, a fourth flip flop
32
for receiving an output signal ldat_dac
4
_b of the third NAND GATE
29
and being synchronized to the clock signal rclk and generating an output signal x
2
b
, a first AND GATE
33
for receiving the output signal x
1
b
and an inverted signal of the output signal x
2
b
of the fourth flip flop
32
, a second OR GATE
34
for receiving an inverted output signal of the first NAND GATE
22
and an output signal of the first AND GATE
33
, a fifth flip flop
35
for receiving an output signal of the second OR GATE
34
as an input signal DA data, an output signal of the first OR GATE
25
as an input signal, an output signal of the second NOR GATE
30
as an enable signal DAB, and generating a load signal LDRDpipe by being synchronized to the clock signal tclk, a third inverting gate
36
for inverting an output of the fifth flip flop
35
and generating an inverted load signal loadRDpipe_b.
An operation of a load signal generating circuit of the above-mentioned prior memory device is explained with reference to a waveform of
FIG. 7
as the following.
The fifth flip flop
35
is synchronized to the clock signal rclk and latches a signal being inputted to an input terminal D in a case that an enable signal DAB is high state, latches a signal of an input terminal Dadata regardless of the clock signal rclk, generates a load signal LDRDpipe as its output signal in a case that an enable signal DAB is in a low state.
In a case of tdac
—
3<3>=1, a first flip flop
23
receives a signal cxff
3
in an ascending edge of the clock signal rclk and generates a signal cas_in_ff
4
delayed by 1 clock, the output signal cas_in_ff
4
of the first flip flop
23
is inputted to an input D of the fifth flip flop
35
through logic gates
24
,
25
. Therefore, the fifth flip flop
35
outputs an output signal LDRDpipe accurately in a next ascending edge of the clock signal rclk, an output signal of the fifth flip flop
35
is inverted via an inverting gate
36
and generates a signal loadRDpipe.
On one hand, in a case of tdac_en<4>=1, a first flip flop
23
receives a signal cxff
3
in an ascending edge of the clock signal rclk and generates a signal cas_in_ff
4
delayed by 1 clock, a second flip flop
27
receives an output signal cas_in_ff
4
via a buffer
26
, generates a signal delayed by 1 clock, i.e., a signal cas_out_ff
4
delayed by 2 clocks than cxff
3
in an ascending edge of a next clock signal rclk.
An output signal cas_out_ff
4
of the second flip flop
27
is inputted to an input D of a third flip flop
30
, synchronized in an ascending edge of the clock signal rclk, outputs an output signal x
2
b
via its output stage Q.
Output signals x
1
b
, x
2
b
of the third and the fourth flip flop
31
,
32
are inputted to a fourth NAND GATE
33
and a third NOR GATE
34
, generate a signal rdpipe with ½ cycle to a fifth flip flop
35
. At this time, as the output signals x
1
b
, x
2
b
of the third and the fourth flip flop
31
,
32
are inputted to a logic gate
33
,
34
and generates a signal rdpipe, the signal rdpipe has a width of ½ cycle and a delay simultaneously.
The signal rdpipe being generated via the third NOR GATE
34
is inputted to an input Dadata of the fifth flip flop
35
, the fifth flip flop
35
latches the signal Dadata and delays it regardless of a clock signal rclk and generates a signal loadRDpipe as an output signal. A signal loadRDpipe generated from a fifth flip flop
35
is inverted via an inverter
36
and generates a signal loadRDpipe_b.
FIG. 4
shows a fifth flip flop
35
in detail. Referring to
FIG. 4
, a transfer gate
361
is turned on by a data enable signal DAB in a DA mode, outputs a signal rdpipe being inputted to an input stage Dadata as a load signal LdRdpipe immediately. When it is a normal operation, the transfer gate
361
generates control signals (sck, sckb), (mck, mck

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