Latched type clock synchronizer with additional 180.degree.-phas

Details Latched type clock synchronizer with additional 180.degree.-phas Latched type clock synchronizer with additional 180.degree.-phas

1998-03-18

1999-07-13

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 395555, 395556, 327261, 327295, G11C 800

Patent

active

059236132

ABSTRACT:
A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks. The multiple pluralities of incrementally delay timing clocks and the latched measurement signal are the inputs to a plurality of phase generators that create a plurality of third timing clocks. Each of a plurality of internal buffers is connected to each of the phase generators to receive one of the third timing clocks. The third timing clock is shaped to create one of the multiple phases of the internal clocks which are then buffered, amplified and transmitted to the integrated circuit.

REFERENCES:
patent: 5065041 (1991-11-01), Moles
patent: 5479128 (1995-12-01), Jan et al.
patent: 5489864 (1996-02-01), Ashuri
patent: 5663767 (1997-09-01), Rumreich et al.
patent: 5663921 (1997-09-01), Pascucci et al.
patent: 5761151 (1998-06-01), Hatakeyama
patent: 5841707 (1998-11-01), Cline et al.
patent: 5867432 (1999-02-01), Toda
T. Saeki et al. "A 2.5ns Clock Access 250 mhz.256mb SPRAM With Synchronous Mirror Delay", IEEE Journal of Solid State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1664.
T. Yamada et al. Capacitive Coupled Bus With Negative Delay Circuit For High Speed and Low Power (10GB/s<500mW) Synchronous DRAM> Digest of Papers for IEEE Symposium on VLSI Circuits, 1996, pp. 112-113.

Affiliated with

Also associated with

Rating

Latched type clock synchronizer with additional 180.degree.-phas does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latched type clock synchronizer with additional 180.degree.-phas, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latched type clock synchronizer with additional 180.degree.-phas will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2283075