Latency time circuit for an S-DRAM

Details Latency time circuit for an S-DRAM Latency time circuit for an S-DRAM

2003-03-11

2004-11-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S230080

Reexamination Certificate

active

06819624

ABSTRACT:

BACKGROUND OF INVENTION
The invention relates to a latency time circuit for an S-DRAM. D-RAM modules are standard memory modules for main memories. D-RAM memories are composed of large-scale integrated transistors and capacitors. In order to obtain the information, the memory contents must be continuously refreshed in this case. A synchronous D-RAM (S-DRAM) allows memory access without any additional waiting cycles. In this case, the data is transferred between the S-DRAM and an external data bus in synchronism with the external clock signal.
FIG. 1
shows an S-DRAM memory module according to the prior art. The S-DRAM memory module is connected to an external control bus, to an external address bus and to an external data bus. The control commands which are applied to the external control bus are read in via command PADS by means of an integrated command receiver, and the received signals are applied, after signal amplification, to a command decoder. The command decoder decodes the applied control commands which, by way of example, have a length of 4 bits, to form internal control commands, for example write (WR) and read (RD). The S-DRAM contains a state machine or sequence controller which controls the internal sequences as a function of the decoded internal control commands. The sequence controller is clocked by a clock signal. For this purpose, an external clock signal CLK
ext
is applied to the S-DRAM and the signal is amplified by means of an integrated clock signal receiver. The amplified clock signal is distributed in the form of a tree in the integrated S-DRAM by means of a clock tree, and is passed via an internal clock line to a sequence controller. The external clock signal is furthermore applied to a delay locked loop DLL. The delay locked loop DLL causes a negative phase shift in the applied external clock signal CLK. The internal DLL clock signal precedes the external clock signal in order that the data is applied to the data pads in synchronism with the external clock signal. The DLL clock signal DLL
CLK
is used for clocking the output signal driver OCD (Off Chip Driver), which is integrated in the S-DRAM for one data path. The delay locked loop DLL is followed by a delay element which forms an internal clock signal (VE-CLK) which is modeled such that it is identical to the external clock signal, that is to say VE-CLK is completely in synchronism with CLK
ext
. The delay element for this purpose compensates for the negative phase shift in the delay locked loop DLL.
The internal sequence controller produces control signals for the internal processing sequence of the S-DRAM as a function of the decoded commands. The sequence controller generates an RAS signal (Row Address Strobe) for driving a row address latch, and a CAS signal (Column Address Select) for driving a column address latch. The row address latch and the column address latch are connected via an internal address bus to an address signal receiver for the S-DRAM Via the external address bus, the S-DRAM receives an external address at the address PADS, with the applied address signals being amplified by an address receiver. In order to save connections, the address is entered in DRAM memories in two steps. In a first step, the row address bits are loaded into the row address latch using the RAS signal. In a second step, the column address bits are loaded into the column address latch using the CAS signal. The address bits are applied respectively to a row decoder and column decoder for access to a memory cell within the memory cell array, which is in the form of a matrix. The row address latch and the column address latch as well as the row and column decoders together form an address signal decoder. The sequence controller produces a refresh control signal in order to refresh the memory cells. A refresh counter, which receives this refresh signal from the sequence controller, produces all the existing rows or row addresses successively, which are then applied to the address bus. To do this, the sequence controller produces an RAS control signal. In this way, all the word lines are activated. Activation of a word line results in all the memory cells which are connected to it being refreshed.
The memory cell array is also connected to read/write amplifiers. The number of read/write amplifiers depends on the memory architecture, on the word length and on the prefetch. In the case of a prefetch 4 with a word length of 32, for example, 128 read/write amplifiers are in operation at the same time. If, by way of example, four independent memory banks are provided, a total of 512 read/write amplifiers are integrated on the memory chip.
One data bit is in each case written to an addressed memory cell, or is read from it, via the read/write amplifiers. The read/write amplifiers are connected via an internal data bus to an internal data path in the S-DRAM. The data in the external data bus is written synchronously via the data path to the S-DRAM and is emitted synchronously from the S-DRAM. The data path is connected to the data PADS of the S-DRAM.
In order to read data, the data path has a data receiver for receiving the externally applied data. An internal driver circuit for the data to be written (WR driver) amplifies the signals in the received data and emits the data that has been read via the internal bus to the read/write amplifiers. The driver circuit WR driver is driven by a write/latency time generator, which is clocked by the internal clock generator VE-CLK. The write/latency time generator is itself connected to a decoder.
For synchronous data emission, the data path contains a data FIFO register, which is followed by an output data driver circuit (OCD driver). The FIFO register is driven by the read/write amplifier by means of an input pointer and by a read/latency generator by means of an output pointer or a delayed data enable signal. The read/latency generator is likewise connected to a decoder.
The two decoders for the read latency time generator and for the write latency time generator are connected via internal control lines to a mode register, in which the data for controlling the operating modes is stored within the S-DRAM. The mode register can be initialized by means of a mode register set command via the internal address bus. The mode register is initialized after switch on. Before any external control commands are applied to the S-DRAM, the mode register is initialized. The mode register contains control data for the CAS latency time, for test modes and for DLL reset.
The sequence controller generates an internal write command PAW as a function of the external control commands, in order to activate the write latency time generator, and generates an internal read command PAR for activation of the read latency time generator.
An internal data path control signal PAR/PAW for the read and write latency time generators, respectively, is generated with a certain signal delay, namely for a decoding time &Dgr;t
DEC
. This decoding time &Dgr;t
DEC
includes a signal delay resulting from the clock signal receiver, the clock signal line tree (clock tree), the downstream latch circuit, resulting from signal delays within the sequence controller, and resulting from signal delay times on the control lines.
t
DEK
=t
CLK
RECEIVER
+t
CLK
TREE
+t
Latch
+t
CMD
Decode
+t
PAR
PRODUCTION
+t
control-line
The generated internal read signal is applied with a short signal delay to the read/write amplifiers, which emit the data to be read out to the internal data bus. The data is passed with a further time delay &Dgr;t
FIFO
from the internal data bus via the FIFO register within the data path to the input of the OCD driver. The OCD driver, or data output driver, emits the data with a further signal delay &Dgr;t
OCD
to the data PADS of the S-DRAM. There is a delay time &Dgr;T between the flank of the external clock signal at which the decoded internal read command RD is applied, and the data output via the data PADS.
FIG. 2
a
shows a latency time generator according to the prior a

Affiliated with

Also associated with

Rating

Latency time circuit for an S-DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latency time circuit for an S-DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latency time circuit for an S-DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3355980