Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-03-01
2011-03-01
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189080, C365S236000
Reexamination Certificate
active
07898900
ABSTRACT:
To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit that combines outputs of second latch circuits; a gate circuit that combines outputs of the first and second wired-OR circuits; and reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit. According to the present invention, as compared to a case that outputs of all the latch circuits are wired-OR connected, output loads are more reduced. Thus, a high signal quality can be obtained.
REFERENCES:
patent: 7345950 (2008-03-01), Fujisawa et al.
patent: 2005/0008113 (2005-01-01), Kokubo et al.
patent: 2008/0043566 (2008-02-01), Fujisawa
patent: 2007-115351 (2007-05-01), None
patent: 2008-047267 (2008-02-01), None
Elpida Memory Inc.
Ho Hoai V
Sughrue & Mion, PLLC
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