Use of silicon block process step to camouflage a false...

Use of silicon block process step to camouflage a false...

Use of silicon block process step to camouflage a false...

Use of silicon germanium and other alloys as the replacement...

Using a first liner layer as a spacer in a semiconductor device

Using an extra boron implant to improve the NMOS reverse narrow

Using an organic layer as an ion implantation mask when forming

Using different gate dielectrics with NMOS and PMOS...

Using different gate dielectrics with NMOS and PMOS...

Using high temperature H2 anneal to recrystallize S/D and...

Using implanted poly-1 to improve charging protection in...

Using NO or N.sub.2 O treatment to generate different oxide thic

Using oxide junction to cut off sub-threshold leakage in...

Using p-type halo implant as ROM cell isolation in flat-cell mas

Using silicate layers for composite semiconductor

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone...

Utilizing amorphorization of polycrystalline structures to...

UV-blocking etch stop layer for reducing UV-induced charging...

UV-blocking layer for reducing UV-induced charging of SONOS...

UV-programmed P-type Mask ROM and fabrication thereof