Using implanted poly-1 to improve charging protection in...

Details Using implanted poly-1 to improve charging protection in... Using implanted poly-1 to improve charging protection in...

2007-03-16

2009-06-30

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21179

Reexamination Certificate

active

07553727

ABSTRACT:
The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.

REFERENCES:
patent: 6362049 (2002-03-01), Cagnina et al.
patent: 6372577 (2002-04-01), Fang
patent: 6432776 (2002-08-01), Ono
patent: 2004/0241948 (2004-12-01), Nieh et al.

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