Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone...

Details Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone... Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone...

2007-01-02

2007-01-02

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S288000, C257SE21679

Reexamination Certificate

active

10917562

ABSTRACT:
The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

REFERENCES:
patent: 6580120 (2003-06-01), Haspeslagh
patent: 6653189 (2003-11-01), Haddad et al.
patent: 6673677 (2004-01-01), Hofmann et al.

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