Utilizing amorphorization of polycrystalline structures to...

Details Utilizing amorphorization of polycrystalline structures to... Utilizing amorphorization of polycrystalline structures to...

2001-03-30

2002-11-19

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S705000, C438S739000

Reexamination Certificate

active

06482688

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of ingrated circuits, and more particularly to a method of fabricating a transistor device having a generally T-shaped gate.
BACKGROUND OF THE INVENTION
MOS type transistors are a fundamental building block within integrated circuits. Consequently, there is a persistent push to make such devices smaller, faster, etc. The switching speed of a transistor is an important characteristic since it dictates, at least in one respect, how fast the circuits which employ such devices operate. Presently, the switching speed of a transistor is not always limited by the channel transit time (i.e., the time required for charge to be transported across the channel); instead, the switching speed sometimes is limited by the time required to charge and discharge the capacitances that exist between the device electrodes and between the interconnecting conductive lines and the substrate.
One way of appreciating the transistor capacitances is through an exemplary cross section, as illustrated in prior art FIG.
1
. The transistor, an NMOS transistor designated at reference numeral
10
, includes a p-type region
12
(sometimes referred to as the body), such as a P-well or substrate in a CMOS type process. The body
12
has an n-type drain region
14
and a source region
18
formed therein. A doped polysilicon gate
22
overlies a thin gate oxide
24
which defines a channel region
26
therebeneath in the body
12
.
An effective circuit diagram illustrating the various capacitances associated with the transistor
10
is illustrated in prior art FIG.
2
and designated at reference numeral
30
. As seen in prior art
FIG. 2
, capacitances exist between the various device electrodes and between the electrodes and the body region. The drain-to-body capacitance (C
db
) and the source-to-body capacitance (C
sb
) are illustrated in prior art FIG.
2
and are referred to often as junction capacitances. The value of the junction capacitances are a function of both the cross sectional area of the junctions as well as the doping concentrations of the regions, respectively. Similarly, the gate-to-drain capacitance (C
gd
) and the gate-to-source capacitance (C
gs
) illustrated in
FIG. 2
are often collectively referred to as a gate overlap capacitance. The value of such capacitances are a function of the gate oxide thickness and the degree of overlap between the gate and source/drain regions, respectively.
Several developments have occurred which are directed to the reduction in the gate-to-drain (C
gd
) and the gate-to-source (C
gs
) capacitances in order to increase device speed. For example, as illustrated in prior art
FIG. 3
a
, after the gate region
22
is defined, an implantation step occurs, by which dopants
40
are implanted into the substrate
12
. Since the implantation of dopants (e.g., n-type dopants for an NMOS transistor) cause lattice damage, a subsequent thermal processing step (sometimes referred to as an anneal) is conducted. The thermal processing causes the dopants
40
to diffuse and the lattice to be repaired, thereby causing the drain and source regions
14
and
18
, respectively, to extend substantially under lateral portions
42
of the gate electrode
22
, as illustrated in prior art
FIG. 3
b
. The extent or distance (e.g., D
gd
illustrated in prior art
FIG. 3
c
) in which the source and drain regions diffuse under the gate contributes to C
gd
and C
gs
, respectively.
As is known, for a parallel plate type capacitor configuration (which the gate-to-source and gate-to-drain capacitances approximate), the capacitance C is a function of the dielectric (∈), the cross sectional area (A) of the parallel plates, and the distance (d) between the plates; C=∈A/d). Therefore, as can be seen in prior art
FIG. 3
c
, an excessive overlap of the gate and the drain/source (D
gd
) negatively contributes to an increase in C
gd
and C
gs
.
One way in which designers have attempted to decrease C
gd
and C
gs
is to form a poly oxide layer over the gate poly, as illustrated in prior art
FIG. 4
a
and designated at reference numeral
50
. That is, after the poly gate
22
has been defined, an oxide
52
is grown around the poly, thereby forming an oxide sidewall
54
on the lateral edges of the poly, having a particular thickness (t). Using the poly oxide
52
, a subsequent implantation of dopants
40
is spaced laterally away from the gate by a distance (t′) which approximates the poly oxide thickness (t). Consequently, any subsequent anneal results in a lesser amount of source/drain under the gate electrode and thus less gate overlap capacitance. Unfortunately, forming poly oxides
52
having thicknesses greater than about 50 Angstroms results in more silicon being consumed which leads to a silicon recess and increased series resistance, which disadvantageously lowers drive current. In addition, as illustrated in prior art
FIG. 4
b
, the implantation dopants
58
are attracted to the poly oxide sidewall
54
, resulting in a poorly controlled dopant loss in the substrate (sometimes referred to as segregation). Due to the segregation and the poor flexibility in fashioning the poly oxide thickness, the poly oxide solution has not served reliably to satisfactorily reduce C
gd
and C
gs
, respectively.
Another solution employed to reduce the C
gd
and C
gd
of transistors is to alter the shape of the gate electrode, for example, by generating a T-shaped gate electrode structure, as illustrated in prior art
FIG. 5
a
and designated at reference numeral
60
. As illustrated in
FIG. 5
a
, the T-shaped gate electrode
60
has a top region
62
which is larger than a bottom region
64
which interfaces with the gate oxide
24
. Consequently, a “gate footprint”
66
which shields the underlying substrate during a self-aligned source/drain implantation is dictated by the larger, top region
62
of the gate electrode
60
. As illustrated in prior art
FIG. 5
a
, this spatial relationship causes the implantation dopants
40
to be spaced further away from the smaller, bottom gate portion
64
. Consequently, during subsequent thermal processing, the lateral diffusion of the drain and source regions
14
and
18
results in a lesser amount of overlap
68
(D
gd
) with respect to the gate electrode, as illustrated in prior art
FIGS. 5
b
-
5
c
, respectively. With a reduction in the overlap (D
gd
or D
gs
) between the gate and the source, and the gate and the drain, respectively, the cross sectional area (A) associated with the parallel plate capacitor model is reduced substantially.
Although the T-shaped gate electrode configuration of
FIGS. 5
a
-
5
c
provides for a favorable reduction in C
gd
and C
gs
, fabricating devices using such a T-shaped gate electrode has proved challenging. For example, one prior art method of fabricating a T-shaped gate electrode employs a multi-step etch process, for example, as illustrated in prior art
FIGS. 6
a
-
6
b
, and designated at reference numeral
70
. Looking to
FIG. 6
a
, a polysilicon layer
72
is etched using a first etch chemistry to generate a generally anisotropic etch profile
74
for a predetermined period of time. Subsequently, as illustrated in prior art
FIG. 6
b
, a second etch chemistry is employed which is generally isotropic, thereby causing an “undercut” in a bottom portion
76
of the polysilicon
72
which causes the feature of interest to have a notch
78
which approximates a T-shape feature when performed symmetrically.
The prior art etch solutions are not desirable because they tacitly utilize the polymer formation on the sides of the gate. The polymer is formed from the deposition of etch products and resist, and the polymer is thicker on the top of the gate than on the bottom thereof. The prior art methods exploit the etch rate difference between the polymer and the polysilicon. However, the process control of the notch depth and height is difficult. Such difficulty is caused by the various etch steps having different polymer formation r

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