Using oxide junction to cut off sub-threshold leakage in...

Details Using oxide junction to cut off sub-threshold leakage in... Using oxide junction to cut off sub-threshold leakage in...

1999-08-06

2001-03-13

Booth, Ricahrd (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S297000, C438S301000

Reexamination Certificate

active

06200836

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to eliminate sub-threshold leakage current in sub-micron gate electrode structures of CMOS devices.
(2) Description of the Prior Art
Recent developments in the design and manufacturing of semiconductor devices have extended the field for Very Large-Scale Integrated (VLSI) devices to Ultra Large-Scale Integrated (ULSI) devices. For ULSI devices the target device feature size is now in the micron and sub-micron range where there is development work taking place relating to deep sub-micron sizes that reach below 0.5 um. The attainment of the sharp reduction in device feature sizes has mainly been accomplished with gradual but significant advances in supporting technologies such as photolithography and improved etching techniques such as Reactive Ion Etching (RIE). These developments have been taking place concurrent with improvements in photo-imaging techniques and advancements in exposure methods and the wavelengths of the exposure sources that now reach into the Deep Ultra Violet range. Special techniques such as the application of special layers of material further improve focusing depth and sharpness of focus in creating images in for instance layers of photoresist that are applied to create interconnect lines, vias, contact openings and the like. These techniques are equally applied in the formation of for instance Complementary Metal Oxide Semiconductor (CMOS) devices.
The technique of creating complementary n-channel and p channel devices has long been known and applied in the semiconductor industry. The salient advantage of these devices is their low power usage due to the fact that two transistors are paired as complementary n-channel and p-channel transistors whereby in either logic state (on/off) of the device, one of the two transistors is off and negligible current is carried through this transistor. The logic elements of Complementary Metal Oxide devices drain significant amounts of current only at the time that these devices switch from one state to another state. Between these transitions the devices draw very little current resulting in low power dissipation for the CMOS device.
A typical n-channel transistor for a CMOS inverter is formed by first forming a p-region (also called tub or well) in the surface of an n-type silicon substrate. Referring to
FIG. 1
a,
there is shown a cross section of a typical MOS transistor that is formed on the surface of a silicon substrate
10
. A layer
12
of gate oxide is first formed over the surface of the substrate
10
, this layer
12
of oxide serves as a stress relieve layer between the gate of the MOS transistor and the silicon surface. A layer of polysilicon or the like is deposited over the layer of gate oxide
12
and patterned and etched to form the structure
14
of the gate electrode. Source and drain regions (
16
and
18
respectively) are then formed self-aligned with and adjacent to the gate electrode
14
by implanting of high-concentration n-type impurities into the surface of the silicon substrate
10
. In the era of ULSI devices, the width of the gate has been reduced to below 0.5 um, the distance between the source and the drain region (the channel length) is correspondingly reduced. This sharp reduction in channel length however leads to a significant increase in the concentration of the electro-magnetic field close to drain region
18
where this drain region interfaces with the underlying silicon substrate
10
. This sharp increase may lead to leakage current between the drain region
18
and the surrounding silicon of substrate
10
. In addition, hot carriers can be created in the silicon of the substrate
10
and can gain sufficient energy to penetrate into the layer of gate oxide
12
underneath the gate structure
14
resulting in impacting the threshold voltage between the gate
14
and the substrate
10
. This may lead to current flow between the gate electrode
14
and the underlying substrate
10
.
To counteract the increase in the electric field, the art has implemented the formation of Lightly Doped Drain (LDD) regions
20
and
22
that are shown in
FIG. 1
b.
The LDD regions
20
and
22
form double off-set regions whereby the source and drain regions now contain high n-type impurity concentrations
16
and
18
and low n-type impurity concentrations
20
and
22
. The principle objective of the LDD regions
20
and
22
is to offset the high concentration of the electric field around the drain region
18
. The regions are symmetrically formed around the gate electrode and consist of low-concentrations of n-type impurities
20
and
22
. The profile of the implanted regions
20
and
22
indicates that the impurity concentrations in the p-n junction change gradually thereby extending to the source and drain regions to attenuate the electric field.
With the creation of the LDD regions
20
and
22
, the breakdown between the drain region
18
and the channel region between the source and the drain region has been eliminated. Hot carriers that could effect the threshold voltage are thereby also eliminated. However, the low concentration regions
20
and
22
form high resistivity regions by their nature of being low concentration impurity regions. Since the current flows between the source and drain regions, the regions
20
and
22
are now parasitic resistances that are connected in series between the source and the drain regions. This lowers the drain current and the n-resistance performance of the transistor thereby reducing the performance of the device. Sidewalls
24
and
26
of the gate electrode structure
14
that have been formed on the surfaces of the low-concentration n-source and drain regions further emphasizing this effect. The high electric field that is in effect around the drain region
18
generates hot carriers, some of these carriers may be injected into the lower portion of the sidewall
26
of the drain region
18
. The region of the silicon surface of the n-type impurity
22
becomes depleted of carriers due to the electric field that is created by the hot carriers that have become trapped in the underlying layer of gate oxide
12
. This results in an increase of the threshold voltage of the transistor thereby having a negative effect on the drain characteristics and ultimately on the reliability of the transistor.
The above indicated problems in the fabrication of LDD CMOS transistors leads to a requirement for alternate methods of creating these devices, methods that counteract the creation of hot carriers and the resulting parasitic resistance. This requirement takes on increased urgency for devices with micron and sub-micron device features where the impact of leakage current is only further emphasized.
U.S. Pat. No. 5,837,571 (Pathak) shows a process for forming FET with multiple dopant I/I and an 0
2
I/I to change the S/D dopant profiles.
U.S. Pat. No. 4,683,637 (Varker et al.), U.S. Pat. No. 5,488,004 (Yang), and U.S. Pat. No. 5,712,173 (Liu et al.) show SOI devices with 0
2
I/I's.
U.S. Pat. No. 4,772,927 (Saito et al.) teaches an 0
2
I/I into S/D regions.
SUMMARY OF THE INVENTION
A principle objective of the invention is to prevent increases in the threshold voltage in MOS devices.
Another objective of the invention is to provide a method to eliminate sub-threshold leakage current in MOS devices.
Yet another objective of the invention is to provide a method to create high-performance MOS transistors that do not have threshold leakage current.
In accordance with the objectives of the invention a new method is provided for the formation of Lightly Doped Drain (LDD) regions in MOS devices. The body of the gate electrode is formed including the self-aligned LDD regions. After the LDD regions have been formed, an oxide implant is performed under an angle into the surface of the substrate on which the MOS device is being formed. This oxide implant forms an oxide layer around the interface between

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