Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-26
2001-11-20
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S522000, C438S523000, C438S592000, C438S664000
Reexamination Certificate
active
06319784
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of simultaneously recrystallizing the source/drain regions and removing native oxide in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
Before metal deposition for silicidation of the source/drain regions, native oxide formed over the source/drain regions must be removed so that lower contact resistance can be obtained. This is usually done using a hydrofluoric acid (HF) dip or by sputter etching. A disadvantage of sputter etching is that plasma damage to the underlying source/drain region may occur. An HF dip does not damage the source/drain region, but is environmentally hazardous.
After source/drain implantation, an annealing process, typically a rapid thermal process (RTP) in nitrogen, must be performed to repair the crystal structure of the silicon in the source/drain regions. It would be desirable to combine the recrystallization and removal of native oxide to be performed simultaneously.
U.S. Pat. No. 5,863,820 to Huang teaches a salicide process. U.S. Pat. No. 5,646,057 to Liu et al teaches a RTP annealing at high temperature followed by annealing at low temperature using H
2
to improve performance. No mention is made of removing native oxide. U.S. Pat. No. 5,418,184 to Girisch teaches adding a hydrogen halide to a nitrogen anneal and a subsequent step to remove native oxide. U.S. Pat. No. 5,219,798 to Kamakura describes a method to prevent recrystallization defects by spraying H
z
on the underside of a substrate in order to cool it during annealing. U.S. Pat. No. 4,522,657 to Rohatgi et al shows a hydrogen ion implantation followed by a low temperature annealing in nitrogen.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for simultaneously annealing a source/drain region and removing an overlying native oxide layer in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for simultaneously annealing a source/drain region and removing an overlying native oxide layer using a H
2
anneal in the fabrication of integrated circuits.
Yet another object is to perform a high temperature H
2
anneal to anneal the source/drain regions and simultaneously remove native oxide.
Yet another object is to perform an in-situ high temperature H
2
anneal to anneal the source/drain regions and simultaneously remove native oxide before a metal layer is deposited.
In accordance with the objects of the invention, a method for simultaneously annealing a source/drain region and removing an overlying native oxide layer using a H
2
anneal in the fabrication of integrated circuits is achieved. Semiconductor device structures are provided in and on a semiconductor substrate wherein the semiconductor device structures include gate electrodes and associated source and drain regions. A resist protective dielectric layer is deposited overlying the semiconductor device structures. The resist protective dielectric layer is etched away where it is not covered by a mask exposing a top surface of the gate and a surface of the semiconductor substrate overlying the source and drain regions wherein a native oxide layer forms on the exposed surfaces. The substrate is annealed using H
2
whereby the native oxide is removed and whereby the exposed surface of the semiconductor substrate is recrystallized. Thereafter, a metal layer is deposited overlying the resist protective dielectric layer and the exposed surface of the semiconductor substrate and silicided. The metal layer is removed where it is not transformed to a metal silicide leaving the metal silicide overlying the gate, source and drain regions to complete fabrication of the integrated circuit device.
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patent: 5418184 (1995-05-01), Girisch
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patent: 6007671 (1999-12-01), Fujimura et al.
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patent: 6020024 (2000-02-01), Maiti et al.
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S. Wolf and R.N. Tauber, “Silicon Processing for the VLSI Era”, vol. 1, p. 520, Lattice Press, Sunset beach, CA, USA, 1986.
Jang Syun-Ming
Yu Mo-Chiun
Ackerman Stephen B.
Chaudhuri Olik
Pike Rosemary L. S.
Rao Shrinivas H.
Saile George O.
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