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Recessed gate transistor structure and method of forming the...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Recessed polysilicon gate structure for a strained silicon...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Recessed structure for shallow trench isolation and salicide pro

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Recessed-gate thin-film transistor with self-aligned lightly...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Recrystallization method of polysilicon film in thin film...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Recycling of a wafer comprising a multi-layer structure...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Reduced boron diffusion by use of a pre-anneal

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced cap layer erosion for borderless contacts

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced cell-to-cell shorting for memory arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced cell-to-cell shorting for memory arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced channel length for a high performance CMOS transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced channel length lightly doped drain transistor using a su

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced contact area of sidewall conductor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced degradation of metal oxide ceramic due to diffusion...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced dielectric breakdown/leakage semiconductor device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Reduced dielectric breakdown/leakage semiconductor device...

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Reduced dielectric constant spacer materials integration for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced dopant deactivation of source/drain extensions using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced hydrogen sidewall spacer oxide

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Reduced mask CMOS salicided process

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