Reduced dielectric constant spacer materials integration for...

Details Reduced dielectric constant spacer materials integration for... Reduced dielectric constant spacer materials integration for...

2006-07-25

2006-07-25

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S306000

Reexamination Certificate

active

07081393

ABSTRACT:
An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.

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patent: 6316348 (2001-11-01), Fu et al.
patent: 6342450 (2002-01-01), Lattard
patent: 6365451 (2002-04-01), Havemann
patent: 6383951 (2002-05-01), Li
patent: 6429477 (2002-08-01), Mandelman et al.
patent: 6528372 (2003-03-01), Lukanc et al.

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