Reduced boron diffusion by use of a pre-anneal

Details Reduced boron diffusion by use of a pre-anneal Reduced boron diffusion by use of a pre-anneal

1998-02-06

2000-12-12

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438299, 438510, 438517, 438680, 438481, 438486, 438514, 438530, 438540, H01L 21336

Patent

active

061598127

ABSTRACT:
A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH.sub.4) is deposited over the surface of the wafer using a chemical vapor deposition (CVD) tool. The deposition of silane is done at 400.degree. C. The temperature is raised in the CVD tool to a temperature in the range of 550.degree. C. to 650.degree. C. and held for 30-60 minutes. This temperature does not affect the thin film of silicon which is formed from the silane, yet provides the necessary thermal cycle to "repair" the crucial first 200 .ANG. to 600 .ANG. of the silicon surface. Normal processing steps, including a rapid thermal anneal for 30 seconds at 1025.degree. C. follow. The RTA is necessary to activate the dopants (arsenic and boron) in the source and drain of the respective devices. The boron dopant species diffuses less during subsequent rapid thermal anneal cycles since the crucial first 200 .ANG. to 600 .ANG. of the silicon surface have been repaired using this preanneal step.

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