Recessed polysilicon gate structure for a strained silicon...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S289000, C438S290000, C438S299000, C438S300000, C438S301000, C438S303000, C438S305000, C438S306000, C438S307000, C438S485000, C438S486000, C438S514000, C438S518000, C438S519000, C438S521000, C438S523000, C438S524000, C438S527000, C438S529000, C438S533000, C438S570000, C438S571000, C438S576000, C438S581000, C438S585000, C438S586000, C438S589000, C438S590000, C438S592000, C438S595000, C438S597000, C438S604000, C438S607000, C438S674000, C438S682000, C438S683000, C438S685000, C257SE21428, C257SE21419

Reexamination Certificate

active

10864952

ABSTRACT:
A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

REFERENCES:
patent: 5461243 (1995-10-01), Ek et al.
patent: 6429061 (2002-08-01), Rim
patent: 6509587 (2003-01-01), Sugiyama et al.
patent: 6605512 (2003-08-01), Kiyota
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6872610 (2005-03-01), Mansoori et al.
patent: 6878592 (2005-04-01), Besser et al.
patent: 6924182 (2005-08-01), Xiang et al.
patent: 2005/0079692 (2005-04-01), Samoilov et al.
patent: 2005/0139872 (2005-06-01), Chidambaram et al.
Gluck, M., et al., “CoSi2and TiSi2for Si/SiGe Heterodevices”, Elseyier Science S.A., 1995, pp. 549-554.
Krivokapic, Z., et al., “Nickel Silicide Metal Gate FDSOI Devices with Improved Gate Oxide Leakage”; IEEE 2002, 4 pages.
Nayak, D. K., et al., “Enhancement-Mode Quantum-Well GexSi1-xPMOS”, IEEE, vol. 12, No. 4, Apr. 1991, pp. 154-156.
Xiang, Qi, et al., “Strained Silicon NMOS with Nickel-Silicide Metal Gate”, Symposium on VLSI Tehcnology Digest of Technical Papers, 2003, 2 pages.
Yeo, Yee-Chia, et al., “Enhanced Performance in Sub-100 nm CMOSFETs Using Strained Epitaxial Silicon-Germanium”, IEDM, 2000, 4 pages.

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