Reduced mask CMOS salicided process

Details Reduced mask CMOS salicided process Reduced mask CMOS salicided process

1998-01-26

1999-11-23

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438231, 438592, H01L 218238

Patent

active

059899506

ABSTRACT:
The present invention includes forming an oxide layer, nitride on a substrate. An ion implantation is performed. A LPD-oxide is formed on P well. Subsequently, an ion implantation to dope phosphorus into the substrate to form N well. Then, the LPD-oxide is removed. The oxide layer and the silicon nitride layer are respectively removed. Subsequently, a thin gate oxide is regrown on the surface of the substrate. A polysilicon layers, a second nitride are deposited on the oxide layer. Polysilicon gates are patterned. An ion implantation is carried out to implant arsenic into the P well. A thin LPD-oxide is forged along the surface of the gate, the substrate on the P well. A thermal anneal process is used to condense the LPD-oxide. Simultaneously, an ultra thin silicon oxynitride layer is formed on the surface of N well. Next, BSG side wall spacers are formed on the side walls of the gates. The silicon nitride layer is removed. Self-align silicide (SALICIDE), polycide are respectively formed on the exposed substrate, gates. Then, an ion implantation is performed. Then, another ion implantation is next used. Finally, ultra shallow junction source and drain are formed adjacent to the gates by using a rapid thermal process (RTP).

REFERENCES:
patent: 5650341 (1997-07-01), Yang et al.
patent: 5668024 (1997-09-01), Tsai et al.
patent: 5670397 (1997-09-01), Chang et al.
patent: 5854101 (1998-12-01), Wu

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