Reduced channel length lightly doped drain transistor using a su

Details Reduced channel length lightly doped drain transistor using a su Reduced channel length lightly doped drain transistor using a su

1998-03-30

1999-10-19

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438289, 438290, 438291, 438305, 438306, 438516, 438525, 438528, 438232, H01L 21336

Patent

active

059703539

ABSTRACT:
A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

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PCT International Search Report, International Application No. PCT/US98/24907, mailed Mar. 26, 1999.
"An approach using a subamorphizing threshold dose silicon implant of optimal energy to achieve shallower junctions", Akif Sultan and Sanjay Banerjee, Journal of Applied Physics, vol. 83, No. 12, 1998 American Institute of Physics, Jun. 15, 1998, pp. 8046-8050.

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