Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-14
2004-11-02
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S232000, C438S302000
Reexamination Certificate
active
06812106
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices with accurately formed submicron features. The present invention has particular applicability in manufacturing high density semiconductor devices with transistors exhibiting reduced dopant deactivation of source/drain extensions.
BACKGROUND ART
The increasing demand for micro-miniaturization requires scaling down various horizontal and vertical dimensions in various device structures. As the transistor source/drain junction depth is scaled down, there is a corresponding scaled increase in the substrate channel doping to maintain a constant electric field in the transistor channel for high speed performance. These objectives are achieved, in part, by not only forming shallow junctions but also forming source/drain extensions with an abrupt junction/dopant profile slope in proximity to the transistor channel in order to reduce penetration of the source/drain dopant into the transistor channel which occurs as the junction/profile slope becomes less abrupt. Such short channel effects result in poor threshold voltage roll-off characteristics for sub-micron devices.
High performance microprocessor applications require rapid speed of semiconductor circuitry. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, as design rules continue to plunge into the deep sub-micron regime, low resistivity interconnect paths become more critical. A common approach to reduce resistivity comprises forming metal silicide layers on deep source/drain regions, as by employing conventional salicide technology. Such salicide technology, however, is conducted at elevated temperatures resulting in dopant deactivation, particularly in the gate electrode and in the source/drain extensions, and attendant short channel effects.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices comprising transistors with reduced dopant deactivation of gate electrodes and source/drain extensions. There also exists a need for methodology enabling the fabrication of semiconductor devices comprising transistors having source/drain extensions with abrupt junction profiles and high operating speed, and the resulting semiconductor devices.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device comprising transistors exhibiting reduced dopant deactivation of source/drain extensions, reduced tunneling current, and high operating speed.
Another advantage of the present invention is a semiconductor device comprising transistors with high impurity concentrations source/drain extensions, reduced tunneling current, and high operation speed.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a dummy gate over a main surface of a substrate; forming deep source/drain regions in the substrate; forming metal silicide layers on the deep source/drain regions; forming a gate dielectric layer over the substrate; removing the dummy gate leaving an opening defined by side surfaces of the dielectric layers; ion implanting to form spaced apart source/drain extension implants into substrate; and laser thermal annealing to activate the source/drain extensions.
Another advantage of the present invention is a semiconductor device comprising: a gate electrode over a main surface of a substrate with a gate dielectric layer therebetween; dielectric sidewall spacers on side surfaces of the gate electrode; deep source/drain regions of the substrate; metal silicide layers on the deep source/drain regions; source/drain extensions extending from the main surface under the sidewall spacers into the substrate, the source/drain extensions comprising: an upper portion at the main surface of the substrate having a first impurity concentration; and a lower portion having a second impurity concentration less than the first impurity concentration.
Embodiments of the present invention comprise angular ion implantation to form spaced apart pre-amorphized regions extending into the substrate to a first depth and then ion implanting impurities to form source/drain extension implants overlapping the pre-amorphized regions extending into the substrate to a second depth greater than the first depth. Embodiments of the present invention further include forming the dummy gate over the substrate with an oxide layer thereunder and oxide sidewall spacers thereon, forming the deep source/drain regions and metal silicide layers thereon, depositing the dielectric layer, planarizing, as by chemical mechanical polishing (CMP), removing the dummy gate and underlying oxide layer, forming dielectric sidewall spacers, such as silicon nitride, on the side surfaces of the dielectric layer in the opening, forming a gate dielectric layer on the main surface of the substrate, and then depositing the gate electrode material. Source/drain extensions formed in accordance with the embodiments of the present invention typically comprise an upper portion with an activated impurity concentration of 5×10
18
to 1×10
20
atoms/cm
3
and a lower portion having an activated impurity concentration of 5×10
17
to 5×10
8
atoms/cm
3
.
Additional advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 6482724 (2002-11-01), Chatterjee
patent: 6600195 (2003-07-01), Nishida et al.
patent: 6645818 (2003-11-01), Sing et al.
Ogle Robert B.
Paton Eric N.
Tabery Cyrus E.
Xiang Qi
Yu Bin
Advanced Micro Devices , Inc.
Vu Hung
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