Reduced contact area of sidewall conductor

Details Reduced contact area of sidewall conductor Reduced contact area of sidewall conductor

2000-09-29

2002-08-06

Fabruy, Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S095000, C438S102000, C438S133000, C438S675000, C257S004000

Reexamination Certificate

active

06429064

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to programmable memory devices.
2. Background
Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM).
Solid state memory devices typically employ micro-electronic circuit elements for each memory bit (e.g., one to four transistors per bit) in memory applications. Since one or more electronic circuit elements are required for each memory bit, these devices may consume considerable chip “real estate” to store a bit of information, which limits the density of a memory chip. The primary “non-volatile” memory element of these devices, such as an EEPROM, typically employ a floating gate field effect transistor device that has limited reprogrammability and which holds a charge on the gate of field effect transistor to store each memory bit. These classes of memory devices are also relatively slow to program.
Phase change memory devices use phase change materials, i.e., materials that can be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element originally developed by Energy Conversion Devices, Inc. of Troy, Mich. utilizes a phase change material that can be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. Typical materials suitable for such application include those utilizing various chalcogenide elements. These electrical memory devices typically do not use field effect transistor devices, but comprise, in the electrical context, a monolithic body of thin film chalcogenide material. As a result, very little chip real estate is required to store a bit of information, thereby providing for inherently high density memory chips. The state change materials are also truly non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until reset as that value represents a physical state of the material (e.g., crystalline or amorphous). Thus, phase change memory materials represent a significant improvement in non-volatile memory.
The phase change memory devices developed by Energy Conversion Devices, Inc. generally include an electrode between a phase change material and a contact, with the phase change material being electrically isolated from the substrate on which it is formed. Such memory devices typically also include an isolation device in series with the phase change material to permit selective programming of the phase change material. Generally, the size of the memory device is directly related to the size of the electrical contact to the phase change material. It would be desirable to develop techniques to reduce the size of the electrode and the corresponding memory device so that, among other benefits, power requirements to program the memory device may be reduced.
One characteristic common to solid state and phase change memory devices is significant power consumption particularly in setting or resetting memory elements. Power consumption is significant, particularly in portable devices that rely on power cells (e.g., batteries). It would be desirable to decrease the power consumption of a memory device.


REFERENCES:
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5789758 (1998-08-01), Reinberg
patent: 5879955 (1999-03-01), Gonzalez et al.
patent: 5920788 (1999-07-01), Reinberg
patent: 5933365 (1999-08-01), Klersy et al.
patent: 5970336 (1999-10-01), Wolstenholme et al.
patent: 5998244 (1999-12-01), Wolstenholme et al.
patent: 6002140 (1999-12-01), Gonzalez et al.
patent: 6031287 (2000-02-01), Harshfield
patent: 6087674 (2000-07-01), Ovshinsky et al.
patent: 6153890 (2000-11-01), Wolstenholme et al.
patent: 6229157 (2001-05-01), Sandhu

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