Reduced channel length for a high performance CMOS transistor

Details Reduced channel length for a high performance CMOS transistor Reduced channel length for a high performance CMOS transistor

1998-06-08

1999-06-29

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438494, 438498, H01L 21336

Patent

active

059181281

ABSTRACT:
An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral length of the gate conductor is reduced by forming a masking layer upon the gate conductor such that only a portion of the gate conductor is covered by the masking layer. The unmasked portion of the gate conductor is then removed to reduce the lateral length of the gate conductor. In this manner, a gate conductor having a lateral length that is significantly less than a lateral length attainable using a photolithographic process may be obtained.

REFERENCES:
patent: 5036017 (1991-07-01), Noda
patent: 5580804 (1996-12-01), Joh
patent: 5654215 (1997-08-01), Gardner et al.
patent: 5656518 (1997-08-01), Gardner et al.
patent: 5672531 (1997-09-01), Gardner et al.
patent: 5801088 (1998-09-01), Gardner et al.

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