Reduced cell-to-cell shorting for memory arrays

Details Reduced cell-to-cell shorting for memory arrays Reduced cell-to-cell shorting for memory arrays

2005-07-26

2008-11-18

Baumeister, Bradley W. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21009, C257SE21648

Reexamination Certificate

active

07452770

ABSTRACT:
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode comprising titanium nitride (TiN) and hemispherical grained (HSG) silicon. The container housing the capacitor is filled with photoresist and then planarized. The TiN layer is then selectively recessed with a peroxide mixture and subsequently the HSG silicon layer is recessed using tetramethyl ammoniumhydroxide. Thus, the bottom electrode is recessed below the level of particles which may overlie the memory cell capacitors and cause shorts by contacting the bottom electrode.

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