Partial silicide gate in sac (self-aligned contact) process

Details Partial silicide gate in sac (self-aligned contact) process Partial silicide gate in sac (self-aligned contact) process

1999-05-17

2001-04-10

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S241000

Reexamination Certificate

active

06214656

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating partial silicide and self-aligned contact processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In deep submicron ULSI technology, low voltage applications and low threshold voltages are required to decrease power consumption and to increase circuit speed. For ease of fabrication, n-doped polysilicon gates have been used for both n-channel and p-channel devices. These buried channel type PMOS devices are quite susceptible to short channel effects. Great improvement can be made if both PMOS and NMOS devices are surface channel types. In the dual gate surface channel CMOS process, where an NMOS and a PMOS gate come together, a silicide layer is formed thereover to reduce resistance and to ensure ohmic contact. Salicide or polycide technology is used in the dual gate process.
In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode. The silicided gate has lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In some processes, such as the self-aligned contact process, it is difficult to incorporate the salicide or polycide gate process because of thermal cycling or auto-doping concerns. That is, if the silicide is formed just after gate definition, the subsequent thermal cycles for driving in LDD and source/drain regions and forming spacers, for example, will cause auto-doping of the gate through the silicide layer or will degrade the resistance of the silicide. It is desired to introduce a partial silicide process to connect a CMOS surface channel gate into a SAC process.
Silicidation has been widely used in the art. Silicidation techniques and self-aligned contacts are discussed in
Silicon Processing for the VLSI Era
, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 144-149 and in
ULSI Technology
, by C. Y. Chang and S. M. Sze, McGraw-Hill, New York, N.Y., c. 1996, pp.397-402 and 487-488. U.S. Pat. No. 5,668,035 to Fang et al and U.S. Pat. No.5,837,601 to Matsumoto teach dual gate processes. U.S. Pat. No. 5,550,079 to Lin teaches forming a nitrogen-containing silicide shunt over dual gate CMOS devices.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for integrating salicide and self-aligned contact processes in the fabrication of dual gate surface channel devices.
Yet another object is to incorporate a partial sulicide process to connect a surface channel CMOS gate into a self-aligned contact process.
In accordance with the objects of the invention, a method for integrating salicide and self-aligned contact processes in the fabrication integrated circuits is achieved. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. A gate oxide layer is provided in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. Ions are implanted into the polysilicon layer to define a surface channel dual gate wherein an NMOS gate area is formed in one device area and a PMOS gate area is formed in an adjoining device area and the junction where the NMOS gate area meets the PMOS gate area forms a CMOS gate area. A hard mask layer is deposited overlying the polysilicon layer. The hard mask layer and polysilicon layer are patterned to form an NMOS gate in the NMOS gate area, a PMOS gate in the PMOS gate area and a CMOS gate in the CMOS gate area wherein the CMOS gate comprises an NMOS gate adjacent to and adjoining a PMOS gate. Spacers are formed on the sidewalls of the gates. Source and drain regions are formed within the semiconductor substrate associated with the gates. Optionally, a liner layer is deposited overlying the gates and associated source and drain regions. The hard mask layer is removed overlying the CMOS gate and overlying one of the NMOS or PMOS gates where a contact is to be made to the gate. A metal layer is deposited overlying the substrate and annealed wherein the metal layer is transformed into a metal silicide layer where it is not underlaid by the hard mask layer. The metal layer that is not transformed into a metal silicide layer is removed. An insulating layer is deposited over the surface of the semiconductor substrate. A self-aligned contact opening is formed through the insulating layer to one of the source and drain regions. A contact opening is formed through the insulating layer to the metal silicide layer overlying the gate where the contact is to be made. A conducting layer is deposited over the semiconductor substrate and within the self-aligned contact opening and within the contact opening and patterned to complete fabrication of the integrated circuit device.


REFERENCES:
patent: 5550079 (1996-08-01), Lin
patent: 5668035 (1997-09-01), Fang et al.
patent: 5792684 (1998-08-01), Lee et al.
patent: 5837601 (1998-11-01), Matsumoto
patent: 5863820 (2000-03-01), Huang
patent: 6037222 (2000-03-01), Huang et al.
Wolf, “Silicon Processing for the VLSI Era”, vol. :2 Process Integration, Lattice Press, Sunset Beach, CA, c.1990, pp. 144-149.
Chang et al., “ULSI Technology”, The McGraw-Hill Companies, Inc., New York, NY, c. 1996, pp. 397-402, and pp. 487-488.

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